LAN9730-ABZJ-TR

{
  "slug": "lan9730-abzj-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Ethernet ICs, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "communication interface chip-uart-485-232",
    "lan9730-abzj-tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "lan9730-abzj-tr.kicad_sym",
    "lan9730-abzj-tr.kicad_mod",
    "lan9730-abzj-tr.glb",
    "lan9730-abzj-tr.step",
    "lan9730-abzj-tr.lbr",
    "docs/hero.png",
    "docs/lan9730-abzj-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lan9730-abzj-tr-hero.glb",
    "lan9730-abzj-tr-hero.overlay.json",
    "lan9730-abzj-tr-etched.glb"
  ],
  "component": {
    "mpn": "LAN9730-ABZJ-TR",
    "manufacturer": "Microchip Tech",
    "package": "QFN-56-EP(8x8)",
    "pin_count": 57,
    "category": "Communication Interface Chip/UART/485/232",
    "subcategory": "Ethernet ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9ff57db225f7abb98b2b7833aae954b2.pdf",
    "parts": {
      "symbol": "lan9730-abzj-tr.kicad_sym",
      "footprint": "lan9730-abzj-tr.kicad_mod",
      "model_3d": "lan9730-abzj-tr-hero.glb",
      "model_3d_plain": "lan9730-abzj-tr-etched.glb",
      "model_3d_step": "lan9730-abzj-tr-etched.step",
      "model_3d_step_plain": "lan9730-abzj-tr.step",
      "lbr": "lan9730-abzj-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C625112",
      "digikey": "LAN9730-ABZJ-TR-ND",
      "mouser": "886-LAN9730-ABZJ-TR"
    },
    "distributor_check": {
      "checked_at": "2026-10-29T01:55:28Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "LAN9730-ABZJ-TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "886-LAN9730-ABZJ-TR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "nPHY_INT",
        "type": "bidirectional",
        "description": "In Internal PHY Mode it outputs the active-high internal PHY interrupt, while in External PHY Mode it is an active-low PHY interrupt input from the external PHY with an internal pull-up."
      },
      {
        "number": "2",
        "name": "TXN",
        "type": "passive",
        "description": "Ethernet transmit data output negative, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled."
      },
      {
        "number": "3",
        "name": "TXP",
        "type": "passive",
        "description": "Ethernet transmit data output positive, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled."
      },
      {
        "number": "4",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3 V analog power supply; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "5",
        "name": "RXN",
        "type": "passive",
        "description": "Ethernet receive data input negative, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled."
      },
      {
        "number": "6",
        "name": "RXP",
        "type": "passive",
        "description": "Ethernet receive data input positive, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled."
      },
      {
        "number": "7",
        "name": "EXRES",
        "type": "passive",
        "description": "Used for the internal bias circuits; connect to an external 12.0 kΩ 1.0% resistor to ground."
      },
      {
        "number": "8",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3 V analog power supply; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "9",
        "name": "VDD12PLL",
        "type": "power_in",
        "description": "+1.2 V Ethernet PLL power that must be connected to VDD12CORE for proper operation."
      },
      {
        "number": "10",
        "name": "HSIC_DATA",
        "type": "bidirectional",
        "description": "Bi-directional DDR data signal synchronous to HSIC_STROBE as defined in the HSIC USB Electrical Specification, Version 1.0."
      },
      {
        "number": "11",
        "name": "HSIC_STROBE",
        "type": "bidirectional",
        "description": "Bi-directional data strobe signal as defined in the HSIC USB Electrical Specification, Version 1.0."
      },
      {
        "number": "12",
        "name": "VDD12A",
        "type": "power_in",
        "description": "+1.2 V HSIC power that must be connected to VDD12CORE for proper operation."
      },
      {
        "number": "13",
        "name": "TEST2",
        "type": "passive",
        "description": "Must always be connected to +3.3 V for proper operation."
      },
      {
        "number": "14",
        "name": "TXER",
        "type": "bidirectional",
        "description": "In External PHY Mode it is an output to the external PHY indicating a transmit error, while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "15",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3 V analog power supply; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "16",
        "name": "USBRBIAS",
        "type": "passive",
        "description": "Sets the HS transmit current level and on-chip termination impedance; connect to an external 12.0 kΩ 1.0% resistor to ground."
      },
      {
        "number": "17",
        "name": "VDD12USBPLL",
        "type": "power_in",
        "description": "+1.2 V USB PLL power that must be connected to VDD12CORE for proper operation."
      },
      {
        "number": "18",
        "name": "XI",
        "type": "input",
        "description": "External 25 MHz crystal input, which may alternatively be driven by a single-ended clock oscillator with XO left unconnected."
      },
      {
        "number": "19",
        "name": "XO",
        "type": "output",
        "description": "External 25 MHz crystal output that should be left unconnected when XI is driven by a single-ended clock oscillator."
      },
      {
        "number": "20",
        "name": "SLEW_TUNE",
        "type": "input",
        "description": "Applies a 30% slew rate boost to the HSIC_DATA and HSIC_STROBE pins when driven high."
      },
      {
        "number": "21",
        "name": "VDD12CORE",
        "type": "power_in",
        "description": "+1.2 V digital core power, supplied by the internal regulator when CORE_REG_EN is tied high, otherwise +1.2 V must be supplied externally."
      },
      {
        "number": "22",
        "name": "MDC/GPIO2",
        "type": "bidirectional",
        "description": "In External PHY Mode it outputs the management clock to the external PHY, while in Internal PHY Mode it is GPIO2, programmable as push-pull, open-drain, or Schmitt-triggered input."
      },
      {
        "number": "23",
        "name": "MDIO/GPIO1",
        "type": "bidirectional",
        "description": "In External PHY Mode it carries management data to and from the external PHY, while in Internal PHY Mode it is GPIO1, programmable as push-pull, open-drain, or Schmitt-triggered input, and it may serve as PME_MODE_SEL."
      },
      {
        "number": "24",
        "name": "nRESET",
        "type": "input",
        "description": "Active-low input that allows external hardware to reset the device; it is pulled high internally and must be driven low for the minimum period in Section 7.5.4 when used."
      },
      {
        "number": "25",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3 V I/O power; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "26",
        "name": "nFDX_LED/GPIO8",
        "type": "bidirectional",
        "description": "Open-drain LED output driven low when the Ethernet link operates in Full-Duplex mode, and by default this pin is configured as GPIO8."
      },
      {
        "number": "27",
        "name": "nLNKA_LED/GPIO9",
        "type": "bidirectional",
        "description": "Open-drain LED output driven low when a valid link is detected and pulsed high for 80 ms on transmit or receive activity, and by default this pin is configured as GPIO9."
      },
      {
        "number": "28",
        "name": "nSPD_LED/GPIO10",
        "type": "bidirectional",
        "description": "Open-drain LED output driven low at 100 Mbs or during auto-negotiation and driven high at 10 Mbs or during line isolation, and by default this pin is configured as GPIO10."
      },
      {
        "number": "29",
        "name": "EECLK",
        "type": "output",
        "description": "Drives the EEPROM clock of the external EEPROM and must be pulled up externally for proper operation."
      },
      {
        "number": "30",
        "name": "EECS",
        "type": "output",
        "description": "Drives the chip select of the external EEPROM, and an external pull-down resistor is recommended because it may tri-state briefly during power-up."
      },
      {
        "number": "31",
        "name": "EEDO/AUTOMDIX_EN",
        "type": "bidirectional",
        "description": "Drives the EEDI input of the external EEPROM, and as the AUTOMDIX_EN strap it sets the default Auto-MDIX setting (0 = disabled, 1 = enabled)."
      },
      {
        "number": "32",
        "name": "EEDI",
        "type": "input",
        "description": "Driven by the EEDO output of the external EEPROM."
      },
      {
        "number": "33",
        "name": "TEST1",
        "type": "passive",
        "description": "Must always be connected to VSS for proper operation."
      },
      {
        "number": "34",
        "name": "PHY_SEL",
        "type": "input",
        "description": "Selects the internal Ethernet PHY (0 = internal PHY used) or the external PHY connected to the MII port (1 = external PHY used)."
      },
      {
        "number": "35",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3 V I/O power; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "36",
        "name": "nTRST/RXD0",
        "type": "input",
        "description": "In Internal PHY Mode it is the active-low JTAG test port reset input, while in External PHY Mode it is receive data 0 input from the external PHY."
      },
      {
        "number": "37",
        "name": "TDO/nPHY_RST",
        "type": "output",
        "description": "In Internal PHY Mode it is the JTAG test data output, while in External PHY Mode it is the active-low PHY reset output."
      },
      {
        "number": "38",
        "name": "TCK/RXD1",
        "type": "input",
        "description": "In Internal PHY Mode it is the JTAG test clock with a maximum operating frequency of 25 MHz, while in External PHY Mode it is receive data 1 input from the external PHY."
      },
      {
        "number": "39",
        "name": "TMS/RXD2",
        "type": "input",
        "description": "In Internal PHY Mode it is the JTAG test mode select, while in External PHY Mode it is receive data 2 input from the external PHY."
      },
      {
        "number": "40",
        "name": "TDI/RXD3",
        "type": "input",
        "description": "In Internal PHY Mode it is the JTAG test data input, while in External PHY Mode it is receive data 3 input from the external PHY."
      },
      {
        "number": "41",
        "name": "RXCLK",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the receiver clock input from the external PHY, while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "42",
        "name": "RXDV",
        "type": "bidirectional",
        "description": "In External PHY Mode it is an input from the external PHY indicating valid data on RXD[3:0], while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "43",
        "name": "TXEN",
        "type": "bidirectional",
        "description": "In External PHY Mode it is an output to the external PHY indicating valid data on TXD[3:0], while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "44",
        "name": "RXER",
        "type": "bidirectional",
        "description": "In External PHY Mode it is an input from the external PHY indicating a receive error in the packet, while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "45",
        "name": "CRS/GPIO3",
        "type": "bidirectional",
        "description": "In External PHY Mode it is a network carrier input from the external PHY, while in Internal PHY Mode GPIO3 is programmable as push-pull, open-drain, or Schmitt-triggered input."
      },
      {
        "number": "46",
        "name": "COL/GPIO0",
        "type": "bidirectional",
        "description": "In External PHY Mode it is a collision-event input from the external PHY, while in Internal PHY Mode GPIO0 is programmable as push-pull, open-drain, or Schmitt-triggered input and may signal PME."
      },
      {
        "number": "47",
        "name": "TXCLK",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the transmitter clock input from the external PHY, while in Internal PHY Mode it can be configured to display the internal MII signal."
      },
      {
        "number": "48",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3 V I/O power; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "49",
        "name": "CORE_REG_EN",
        "type": "passive",
        "description": "Tie low to VSS to disable the internal core regulator (then +1.2 V must be supplied externally), or tie high to +3.3 V to enable it."
      },
      {
        "number": "50",
        "name": "VDD12CORE",
        "type": "power_in",
        "description": "+1.2 V digital core power, supplied by the internal regulator when CORE_REG_EN is tied high, otherwise +1.2 V must be supplied externally."
      },
      {
        "number": "51",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3 V I/O power; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "52",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3 V I/O power; refer to Chapter 3.0 for connection information."
      },
      {
        "number": "53",
        "name": "TXD3/GPIO7/50DRIVER_EN",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the TXD3 output to the external PHY, while in Internal PHY Mode it is GPIO7, and the 50DRIVER_EN strap selects 40 Ω (0) or 50 Ω (1) output impedance for HSIC_DATA and HSIC_STROBE."
      },
      {
        "number": "54",
        "name": "TXD2/GPIO6/PORT_SWAP",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the TXD2 output to the external PHY, while in Internal PHY Mode it is GPIO6, and the PORT_SWAP strap swaps the HSIC_DATA and HSIC_STROBE functions when set to 1."
      },
      {
        "number": "55",
        "name": "TXD1/GPIO5/RMT_WKP",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the TXD1 output to the external PHY, while in Internal PHY Mode it is GPIO5, and the RMT_WKP strap enables remote wakeup support in default descriptor values when set to 1 (overridden by EEPROM)."
      },
      {
        "number": "56",
        "name": "TXD0/GPIO4/EEP_DISABLE",
        "type": "bidirectional",
        "description": "In External PHY Mode it is the TXD0 output to the external PHY, while in Internal PHY Mode it is GPIO4, and the EEP_DISABLE strap prevents EEPROM autoload when set to 1."
      },
      {
        "number": "57",
        "name": "VSS",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN suffix (ABZJ-TR) and its mapping to the 56-VQFN package are not stated in the extracted page; Pin 1 nPHY_INT, pins 14, 22, 23, 41-47, 53-56 and others are multi-function and have different buffe; The exposed pad has no printed number in the extracted text. It is listed as 'EP' here as a placehol",
          "exposed pad 57 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint",
          "26/57 pins cited to the wrong page (name found elsewhere): ['13:TEST2@p22', '18:XI@p22', '19:XO@p22', '21:VDD12CORE@p21']"
        ],
        "pages_sent": 33,
        "cost_usd": 0.1663,
        "at": "2026-10-29T01:55:06"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/9ff57db225f7abb98b2b7833aae954b2.pdf",
        "pages": 222,
        "sha256": "d2a4d6bcf3f6d659",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 57,
        "described": 57,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lan9730-abzj-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          8.0,
          8.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "54eb482f12c9d8b70c1bfc78306a1c34f412f3556e225cbd097840e5abdb7981",
        "checked": "2026-10-29",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lan9730-abzj-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          8.0,
          8.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9bb066913ba10cd0cfbae8eefc606f26c4cff34af66530b420ed6e3610bd5b5a",
        "checked": "2026-10-29",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "RT (56L VQFN, 8x8 mm body, 5.9x5.9 mm exposed pad, Microchip drawing C04-375A)",
      "source_page": 214,
      "D": {
        "nom_mm": 7.75,
        "range_mm": [
          7.65,
          7.85
        ]
      },
      "E1": {
        "nom_mm": 7.75,
        "range_mm": [
          7.65,
          7.85
        ]
      },
      "e": {
        "nom_mm": 0.5,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 0.85,
        "range_mm": [
          0.7,
          1.0
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "lan9730-abzj-tr.step",
        "verdict": "PASS",
        "reasons": [
          "height within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}