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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

LAN9730-ABZJ-TR

Microchip Tech · Ethernet ICs · QFN-56-EP(8x8)

LAN9730-ABZJ-TR from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	nPHY_INT	bidirectional	In Internal PHY Mode it outputs the active-high internal PHY interrupt, while in External PHY Mode it is an active-low PHY interrupt input from the external PHY with an internal pull-up.
2	TXN	passive	Ethernet transmit data output negative, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled.
3	TXP	passive	Ethernet transmit data output positive, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled.
4	VDD33A	power_in	+3.3 V analog power supply; refer to Chapter 3.0 for connection information.
5	RXN	passive	Ethernet receive data input negative, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled.
6	RXP	passive	Ethernet receive data input positive, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled.
7	EXRES	passive	Used for the internal bias circuits; connect to an external 12.0 kΩ 1.0% resistor to ground.
8	VDD33A	power_in	+3.3 V analog power supply; refer to Chapter 3.0 for connection information.
9	VDD12PLL	power_in	+1.2 V Ethernet PLL power that must be connected to VDD12CORE for proper operation.
10	HSIC_DATA	bidirectional	Bi-directional DDR data signal synchronous to HSIC_STROBE as defined in the HSIC USB Electrical Specification, Version 1.0.
11	HSIC_STROBE	bidirectional	Bi-directional data strobe signal as defined in the HSIC USB Electrical Specification, Version 1.0.
12	VDD12A	power_in	+1.2 V HSIC power that must be connected to VDD12CORE for proper operation.
13	TEST2	passive	Must always be connected to +3.3 V for proper operation.
14	TXER	bidirectional	In External PHY Mode it is an output to the external PHY indicating a transmit error, while in Internal PHY Mode it can be configured to display the internal MII signal.
15	VDD33A	power_in	+3.3 V analog power supply; refer to Chapter 3.0 for connection information.
16	USBRBIAS	passive	Sets the HS transmit current level and on-chip termination impedance; connect to an external 12.0 kΩ 1.0% resistor to ground.
17	VDD12USBPLL	power_in	+1.2 V USB PLL power that must be connected to VDD12CORE for proper operation.
18	XI	input	External 25 MHz crystal input, which may alternatively be driven by a single-ended clock oscillator with XO left unconnected.
19	XO	output	External 25 MHz crystal output that should be left unconnected when XI is driven by a single-ended clock oscillator.
20	SLEW_TUNE	input	Applies a 30% slew rate boost to the HSIC_DATA and HSIC_STROBE pins when driven high.
21	VDD12CORE	power_in	+1.2 V digital core power, supplied by the internal regulator when CORE_REG_EN is tied high, otherwise +1.2 V must be supplied externally.
22	MDC/GPIO2	bidirectional	In External PHY Mode it outputs the management clock to the external PHY, while in Internal PHY Mode it is GPIO2, programmable as push-pull, open-drain, or Schmitt-triggered input.
23	MDIO/GPIO1	bidirectional	In External PHY Mode it carries management data to and from the external PHY, while in Internal PHY Mode it is GPIO1, programmable as push-pull, open-drain, or Schmitt-triggered input, and it may serve as PME_MODE_SEL.
24	nRESET	input	Active-low input that allows external hardware to reset the device; it is pulled high internally and must be driven low for the minimum period in Section 7.5.4 when used.
25	VDD33IO	power_in	+3.3 V I/O power; refer to Chapter 3.0 for connection information.
26	nFDX_LED/GPIO8	bidirectional	Open-drain LED output driven low when the Ethernet link operates in Full-Duplex mode, and by default this pin is configured as GPIO8.
27	nLNKA_LED/GPIO9	bidirectional	Open-drain LED output driven low when a valid link is detected and pulsed high for 80 ms on transmit or receive activity, and by default this pin is configured as GPIO9.
28	nSPD_LED/GPIO10	bidirectional	Open-drain LED output driven low at 100 Mbs or during auto-negotiation and driven high at 10 Mbs or during line isolation, and by default this pin is configured as GPIO10.
29	EECLK	output	Drives the EEPROM clock of the external EEPROM and must be pulled up externally for proper operation.
30	EECS	output	Drives the chip select of the external EEPROM, and an external pull-down resistor is recommended because it may tri-state briefly during power-up.
31	EEDO/AUTOMDIX_EN	bidirectional	Drives the EEDI input of the external EEPROM, and as the AUTOMDIX_EN strap it sets the default Auto-MDIX setting (0 = disabled, 1 = enabled).
32	EEDI	input	Driven by the EEDO output of the external EEPROM.
33	TEST1	passive	Must always be connected to VSS for proper operation.
34	PHY_SEL	input	Selects the internal Ethernet PHY (0 = internal PHY used) or the external PHY connected to the MII port (1 = external PHY used).
35	VDD33IO	power_in	+3.3 V I/O power; refer to Chapter 3.0 for connection information.
36	nTRST/RXD0	input	In Internal PHY Mode it is the active-low JTAG test port reset input, while in External PHY Mode it is receive data 0 input from the external PHY.
37	TDO/nPHY_RST	output	In Internal PHY Mode it is the JTAG test data output, while in External PHY Mode it is the active-low PHY reset output.
38	TCK/RXD1	input	In Internal PHY Mode it is the JTAG test clock with a maximum operating frequency of 25 MHz, while in External PHY Mode it is receive data 1 input from the external PHY.
39	TMS/RXD2	input	In Internal PHY Mode it is the JTAG test mode select, while in External PHY Mode it is receive data 2 input from the external PHY.
40	TDI/RXD3	input	In Internal PHY Mode it is the JTAG test data input, while in External PHY Mode it is receive data 3 input from the external PHY.
41	RXCLK	bidirectional	In External PHY Mode it is the receiver clock input from the external PHY, while in Internal PHY Mode it can be configured to display the internal MII signal.
42	RXDV	bidirectional	In External PHY Mode it is an input from the external PHY indicating valid data on RXD[3:0], while in Internal PHY Mode it can be configured to display the internal MII signal.
43	TXEN	bidirectional	In External PHY Mode it is an output to the external PHY indicating valid data on TXD[3:0], while in Internal PHY Mode it can be configured to display the internal MII signal.
44	RXER	bidirectional	In External PHY Mode it is an input from the external PHY indicating a receive error in the packet, while in Internal PHY Mode it can be configured to display the internal MII signal.
45	CRS/GPIO3	bidirectional	In External PHY Mode it is a network carrier input from the external PHY, while in Internal PHY Mode GPIO3 is programmable as push-pull, open-drain, or Schmitt-triggered input.
46	COL/GPIO0	bidirectional	In External PHY Mode it is a collision-event input from the external PHY, while in Internal PHY Mode GPIO0 is programmable as push-pull, open-drain, or Schmitt-triggered input and may signal PME.
47	TXCLK	bidirectional	In External PHY Mode it is the transmitter clock input from the external PHY, while in Internal PHY Mode it can be configured to display the internal MII signal.
48	VDD33IO	power_in	+3.3 V I/O power; refer to Chapter 3.0 for connection information.
49	CORE_REG_EN	passive	Tie low to VSS to disable the internal core regulator (then +1.2 V must be supplied externally), or tie high to +3.3 V to enable it.
50	VDD12CORE	power_in	+1.2 V digital core power, supplied by the internal regulator when CORE_REG_EN is tied high, otherwise +1.2 V must be supplied externally.
51	VDD33IO	power_in	+3.3 V I/O power; refer to Chapter 3.0 for connection information.
52	VDD33IO	power_in	+3.3 V I/O power; refer to Chapter 3.0 for connection information.
53	TXD3/GPIO7/50DRIVER_EN	bidirectional	In External PHY Mode it is the TXD3 output to the external PHY, while in Internal PHY Mode it is GPIO7, and the 50DRIVER_EN strap selects 40 Ω (0) or 50 Ω (1) output impedance for HSIC_DATA and HSIC_STROBE.
54	TXD2/GPIO6/PORT_SWAP	bidirectional	In External PHY Mode it is the TXD2 output to the external PHY, while in Internal PHY Mode it is GPIO6, and the PORT_SWAP strap swaps the HSIC_DATA and HSIC_STROBE functions when set to 1.
55	TXD1/GPIO5/RMT_WKP	bidirectional	In External PHY Mode it is the TXD1 output to the external PHY, while in Internal PHY Mode it is GPIO5, and the RMT_WKP strap enables remote wakeup support in default descriptor values when set to 1 (overridden by EEPROM).
56	TXD0/GPIO4/EEP_DISABLE	bidirectional	In External PHY Mode it is the TXD0 output to the external PHY, while in Internal PHY Mode it is GPIO4, and the EEP_DISABLE strap prevents EEPROM autoload when set to 1.
57	VSS	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Communication Interface Chip/UART/485/232
Pins	57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
+3.3 V supply voltage absolute maximum (VDD33IO, VDD33A)		0		3.6	V	Note 7-1	195
+1.2 V supply voltage absolute maximum (VDD12CORE, VDD12PLL, VDD12USBPLL, VDD12A)		0		1.5	V	Note 7-1	195
Negative voltage on input signal pins with respect to ground		-0.5			V	Note 7-3: does not apply to EXRES, USBRBIAS, HSIC_STROBE, HSIC_DATA	195
Storage temperature		-55		150	°C		195
+3.3 V supply voltage tolerance (VDD33IO, VDD33A), nominal +3.3 V	VDD33IO, VDD33A	-10		10	%	Recommended operating condition; nominal 3.3 V	195
+1.2 V supply voltage tolerance (VDD12CORE, VDD12PLL, VDD12USBPLL, VDD12A), nominal +1.2 V		-5		10	%	Recommended operating condition; nominal 1.2 V	195
Ambient operating temperature in still air, commercial version	TA	0		70	°C	Note 7-4: commercial version	195
Ambient operating temperature in still air, industrial version	TA	-40		85	°C	Note 7-4: industrial version (LAN9730i)	195
Input leakage, IS type input buffer	IIH	-10		10	µA	VIN = VSS or VDD33IO	199
Low output level, O8 type buffers	VOL			0.4	V	IOL = 8 mA	199
Low output level, OD8 type buffer	VOL			0.4	V	IOL = 8 mA	199
Low output level, O12 type buffers	VOL			0.4	V	IOL = 12 mA	199
Low output level, OD12 type buffer	VOL			0.4	V	IOL = 12 mA	199
HSIC I/O pad drive strength	OD	38	40	42	Ohm	50DRIVER_EN = VSS	199
HSIC I/O pad drive strength	OD	47.5	50	52.5	Ohm	50DRIVER_EN = +3.3 V	199
Input leakage, HSIC type buffer	IIH	-10		10	µA	VIN = VSS or VDD33IO	199
Low input level, ICLK type buffer (XI)	VILI			0.35	V	Note 7-6: XI can optionally be driven from a 25 MHz single-ended clock oscillator	200
High input level, ICLK type buffer (XI)	VIHI	0.8			V	Note 7-6: XI can optionally be driven from a 25 MHz single-ended clock oscillator	200
Peak differential output voltage high (100BASE-TX)	VPPH	950		1050	mVpk	Note 7-7: measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	200
Peak differential output voltage low (100BASE-TX)	VPPL	-1050		-950	mVpk	Note 7-7: measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	200
Signal amplitude symmetry (100BASE-TX)	VSS	98		102	%	Note 7-7	200
Signal rise and fall time (100BASE-TX)	TRF	3		5	ns	Note 7-7	200
Rise and fall symmetry (100BASE-TX)	TRFS			0.5	ns	Note 7-7	200
Duty cycle distortion (100BASE-TX)	DCD	35	50	65	%	Note 7-8: offset from 16 ns pulse width at 50% of pulse peak	200
Overshoot and undershoot (100BASE-TX)	VOS			5	%		200
Transmitter peak differential output voltage (10BASE-T)	VOUT	2.2	2.5	2.8	V	Note 7-10: min/max guaranteed with 100 Ω resistive load	200
Receiver differential squelch threshold (10BASE-T)	VDS	300	420	585	mV		200
TCK clock period	ttckp	66.67			ns	JTAG timing	209
TDI, TMS setup to TCK rising edge	tsu	10			ns	JTAG timing	209
TDI, TMS hold from TCK rising edge	th	10			ns	JTAG timing	209
TDO output valid from TCK falling edge	tdov			16	ns	JTAG timing	209
TDO output invalid from TCK falling edge	tdoinvld	0			ns	JTAG timing	209

CAD (KiCad official)

Symbol: LAN9730-ABZJ-TR
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
3D model files: lan9730-abzj-tr-etched.step / lan9730-abzj-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9730-abzj-tr.step / lan9730-abzj-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (222 pp, sha256 d2a4d6bcf3f6d659, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF