LAN9500AI-ABZJ

{
  "slug": "lan9500ai-abzj",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech USB Converters, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "lan9500ai-abzj",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lan9500ai-abzj.kicad_sym",
    "lan9500ai-abzj.kicad_mod",
    "lan9500ai-abzj.glb",
    "lan9500ai-abzj.step",
    "lan9500ai-abzj.lbr",
    "docs/hero.png",
    "docs/lan9500ai-abzj-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lan9500ai-abzj-hero.glb",
    "lan9500ai-abzj-hero.overlay.json",
    "lan9500ai-abzj-etched.glb"
  ],
  "component": {
    "mpn": "LAN9500AI-ABZJ",
    "manufacturer": "Microchip Tech",
    "package": "QFN-56-EP(8x8)",
    "pin_count": 57,
    "category": "Interface",
    "subcategory": "USB Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8553195571167834112",
    "parts": {
      "symbol": "lan9500ai-abzj.kicad_sym",
      "footprint": "lan9500ai-abzj.kicad_mod",
      "model_3d": "lan9500ai-abzj-hero.glb",
      "model_3d_plain": "lan9500ai-abzj-etched.glb",
      "model_3d_step": "lan9500ai-abzj-etched.step",
      "model_3d_step_plain": "lan9500ai-abzj.step",
      "lbr": "lan9500ai-abzj.lbr"
    },
    "distributor_links": {
      "lcsc": "C220246",
      "digikey": "LAN9500AI-ABZJ-ND",
      "mouser": "886-LAN9500AI-ABZJ"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T02:46:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "LAN9500AI-ABZJ-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "886-LAN9500AI-ABZJ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "nPHY_INT",
        "type": "output",
        "description": "In internal PHY mode it outputs the active-high internal PHY interrupt signal; in external PHY mode it is an active-low PHY interrupt input from the external PHY."
      },
      {
        "number": "2",
        "name": "TXN",
        "type": "bidirectional",
        "description": "Ethernet TX data output negative, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled."
      },
      {
        "number": "3",
        "name": "TXP",
        "type": "bidirectional",
        "description": "Ethernet TX data output positive, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled."
      },
      {
        "number": "4",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3V analog power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "5",
        "name": "RXN",
        "type": "bidirectional",
        "description": "Ethernet RX data input negative, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled."
      },
      {
        "number": "6",
        "name": "RXP",
        "type": "bidirectional",
        "description": "Ethernet RX data input positive, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "No-connect on LAN9500A/LAN9500Ai; the pin must be left floating for normal device operation."
      },
      {
        "number": "8",
        "name": "EXRES",
        "type": "passive",
        "description": "External PHY bias resistor connection to ground; use 12.0K 1.0% for LAN9500A/LAN9500Ai."
      },
      {
        "number": "9",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3V analog power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "10",
        "name": "VDDPLL",
        "type": "power_in",
        "description": "Ethernet PLL power supply that must be connected to VDDCORE for proper operation."
      },
      {
        "number": "11",
        "name": "USBDM",
        "type": "bidirectional",
        "description": "USB D- analog bidirectional signal whose function may be swapped with USBDP via the PORT_SWAP configuration strap."
      },
      {
        "number": "12",
        "name": "USBDP",
        "type": "bidirectional",
        "description": "USB D+ analog bidirectional signal whose function may be swapped with USBDM via the PORT_SWAP configuration strap."
      },
      {
        "number": "13",
        "name": "TEST2",
        "type": "passive",
        "description": "Test pin that must always be connected to VSS for proper operation."
      },
      {
        "number": "14",
        "name": "NC",
        "type": "unconnected",
        "description": "No-connect pin that must be left floating for normal device operation."
      },
      {
        "number": "15",
        "name": "VDD33A",
        "type": "power_in",
        "description": "+3.3V analog power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "16",
        "name": "USBRBIAS",
        "type": "passive",
        "description": "External USB bias resistor that sets HS transmit current and on-chip termination; connect to an external 12K 1.0% resistor to ground."
      },
      {
        "number": "17",
        "name": "VDDUSBPLL",
        "type": "power_in",
        "description": "USB PLL supply that must be connected to VDDCORE for proper operation."
      },
      {
        "number": "18",
        "name": "XI",
        "type": "input",
        "description": "External 25 MHz crystal input, which may also be driven by a single-ended clock oscillator with XO left unconnected."
      },
      {
        "number": "19",
        "name": "XO",
        "type": "output",
        "description": "External 25 MHz crystal output that must be left unconnected when XI is driven by a single-ended clock oscillator."
      },
      {
        "number": "20",
        "name": "VBUS_DET",
        "type": "input",
        "description": "5V-tolerant input detecting upstream bus power that must be tied to VDD33IO for bus-powered applications; on LAN9500A/LAN9500Ai it may also signal bus power availability in PME mode."
      },
      {
        "number": "21",
        "name": "VDDCORE",
        "type": "power_out",
        "description": "Digital core power supply output from the internal core regulator; refer to Section 4.0 for connection information."
      },
      {
        "number": "22",
        "name": "MDC/GPIO2",
        "type": "bidirectional",
        "description": "In internal PHY mode it is the PHY management clock or a programmable GPIO2 (push-pull, open-drain, or Schmitt input); in external PHY mode it outputs the management clock to the external PHY."
      },
      {
        "number": "23",
        "name": "MDIO/GPIO1",
        "type": "bidirectional",
        "description": "In external PHY mode it carries management data to/from the external PHY, while in internal PHY mode it is a programmable GPIO1; on LAN9500A/LAN9500Ai it may serve as the PME_MODE_SEL input."
      },
      {
        "number": "24",
        "name": "nRESET",
        "type": "input",
        "description": "Active-low system reset input that allows external hardware to reset the device; on LAN9500A/LAN9500Ai it may signal PME_CLEAR when PME mode is in effect."
      },
      {
        "number": "25",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V I/O power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "26",
        "name": "nFDX_LED/GPIO8",
        "type": "bidirectional",
        "description": "Open-drain Ethernet full-duplex indicator LED pin driven low (LED on) when the link operates in full-duplex mode, also usable as GPIO8 (12 mA sink open-drain)."
      },
      {
        "number": "27",
        "name": "nLNKA_LED/GPIO9",
        "type": "bidirectional",
        "description": "Open-drain Ethernet link activity LED pin driven low (LED on) when a valid link is detected and pulsed for activity, also usable as GPIO9 (12 mA sink open-drain)."
      },
      {
        "number": "28",
        "name": "nSPD_LED/GPIO10",
        "type": "bidirectional",
        "description": "Open-drain Ethernet speed indicator LED pin driven low (LED on) at 100 Mb/s or during auto-negotiation and high at 10 Mb/s, also usable as GPIO10."
      },
      {
        "number": "29",
        "name": "EECLK/PWR_SEL",
        "type": "output",
        "description": "Drives the clock of the external EEPROM; the PWR_SEL configuration strap sets the default power mode (0 = bus powered, 1 = self powered) when no EEPROM is present."
      },
      {
        "number": "30",
        "name": "EECS",
        "type": "output",
        "description": "Drives the chip select of the external EEPROM; an external pull-down is recommended because it may tri-state briefly during power-up."
      },
      {
        "number": "31",
        "name": "EEDO/AUTOMDIX_EN",
        "type": "output",
        "description": "Drives the EEDI input of the external EEPROM; the AUTOMDIX_EN strap sets the default Auto-MDIX (0 = disabled, 1 = enabled)."
      },
      {
        "number": "32",
        "name": "EEDI",
        "type": "input",
        "description": "Input driven by the EEDO output of the external EEPROM."
      },
      {
        "number": "33",
        "name": "TEST3",
        "type": "passive",
        "description": "Test pin that must always be connected to VSS for proper operation."
      },
      {
        "number": "34",
        "name": "PHY_SEL",
        "type": "input",
        "description": "Selects the internal Ethernet PHY (0) or the external PHY connected to the MII port (1)."
      },
      {
        "number": "35",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V I/O power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "36",
        "name": "nTRST/RXD0",
        "type": "input",
        "description": "Active-low JTAG test port reset input in internal PHY mode, or the receive data 0 input from the external PHY in external PHY mode."
      },
      {
        "number": "37",
        "name": "TDO/nPHY_RST",
        "type": "output",
        "description": "JTAG test data output in internal PHY mode, or an active-low PHY reset output in external PHY mode."
      },
      {
        "number": "38",
        "name": "TCK/RXD1",
        "type": "input",
        "description": "JTAG test clock input with a maximum operating frequency of 25 MHz in internal PHY mode, or the receive data 1 input in external PHY mode."
      },
      {
        "number": "39",
        "name": "TMS/RXD2",
        "type": "input",
        "description": "JTAG test mode select input in internal PHY mode, or the receive data 2 input from the external PHY in external PHY mode."
      },
      {
        "number": "40",
        "name": "TDI/RXD3",
        "type": "input",
        "description": "JTAG test data input in internal PHY mode, or the receive data 3 input from the external PHY in external PHY mode."
      },
      {
        "number": "41",
        "name": "RXCLK",
        "type": "bidirectional",
        "description": "Receive clock that is the receiver clock input from the external PHY in external PHY mode, or an MII signal visibility output in internal PHY mode."
      },
      {
        "number": "42",
        "name": "RXDV",
        "type": "bidirectional",
        "description": "Receive data valid that is input from the external PHY in external PHY mode and indicates valid data on RXD[3:0]."
      },
      {
        "number": "43",
        "name": "TXEN",
        "type": "bidirectional",
        "description": "Transmit enable that is an output to the external PHY in external PHY mode and indicates valid data on TXD[3:0]."
      },
      {
        "number": "44",
        "name": "RXER",
        "type": "bidirectional",
        "description": "Receive error that is input from the external PHY in external PHY mode and indicates a receive error in the packet."
      },
      {
        "number": "45",
        "name": "CRS/GPIO3",
        "type": "bidirectional",
        "description": "Carrier sense that is input from the external PHY in external PHY mode and indicates a network carrier, or programmable GPIO3 in internal PHY mode."
      },
      {
        "number": "46",
        "name": "COL/GPIO0",
        "type": "bidirectional",
        "description": "MII collision detect input from the external PHY in external PHY mode, or programmable GPIO0 in internal PHY mode, which on LAN9500A/LAN9500Ai may signal PME."
      },
      {
        "number": "47",
        "name": "TXCLK",
        "type": "bidirectional",
        "description": "Transmitter clock that is the transmitter clock input from the external PHY in external PHY mode."
      },
      {
        "number": "48",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V I/O power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "49",
        "name": "TEST1",
        "type": "passive",
        "description": "Test pin that must always be connected to VDD33IO for proper operation."
      },
      {
        "number": "50",
        "name": "VDDCORE",
        "type": "power_out",
        "description": "Digital core power supply output from the internal core regulator; refer to Section 4.0 for connection information."
      },
      {
        "number": "51",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V I/O power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "52",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V I/O power supply; refer to the device reference schematics for connection information."
      },
      {
        "number": "53",
        "name": "TXD3/GPIO7/EEP_SIZE",
        "type": "bidirectional",
        "description": "Transmit data 3 output to the external PHY in external mode, or programmable GPIO7 in internal mode; the EEP_SIZE strap selects a 128-byte (0) or 256/512-byte (1) EEPROM."
      },
      {
        "number": "54",
        "name": "TXD2/GPIO6/PORT_SWAP",
        "type": "bidirectional",
        "description": "Transmit data 2 output to the external PHY in external mode, or programmable GPIO6 in internal mode; the PORT_SWAP strap swaps the USBDP and USBDM mapping."
      },
      {
        "number": "55",
        "name": "TXD1/GPIO5/RMT_WKP",
        "type": "bidirectional",
        "description": "Transmit data 1 output to the external PHY in external mode, or programmable GPIO5 in internal mode; the RMT_WKP strap enables (1) or disables (0) remote wakeup default descriptor values, overridden by the EEPROM."
      },
      {
        "number": "56",
        "name": "TXD0/GPIO4/EEP_DISABLE",
        "type": "bidirectional",
        "description": "Transmit data 0 output to the external PHY in external mode, or programmable GPIO4 in internal mode; the EEP_DISABLE strap prevents EEPROM autoload when set to 1."
      },
      {
        "number": "57",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Exposed pad on the package bottom (must be connected to VSS / ground) is not given a numbered pin in; Pin types are given per mode in the datasheet (internal PHY vs external PHY, and LAN9500 vs LAN9500A; Pins 20, 23, 24, 27, 28 and 46 carry PME-related functions that apply only to LAN9500A/LAN9500Ai (th",
          "exposed pad 57 added from the footprint",
          "22/57 pins cited to the wrong page (name found elsewhere): ['13:TEST2@p19', '19:XO@p20', '26:nFDX_LED/GPIO8@p18', '27:nLNKA_LED/GPIO9@p18']"
        ],
        "pages_sent": 30,
        "cost_usd": 0.1694,
        "at": "2026-10-18T02:44:22"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8553195571167834112",
        "pages": 214,
        "sha256": "57c7730da3b38584",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 57,
        "described": 57,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lan9500ai-abzj.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          8.0,
          8.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "54eb482f12c9d8b70c1bfc78306a1c34f412f3556e225cbd097840e5abdb7981",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lan9500ai-abzj-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          8.0,
          8.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "fda142f845d13d08df75bde052401231145a427f9290a79a6edd1d95daec8d1e",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}