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LAN9500AI-ABZJ

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Microchip Tech USB Converters, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LAN9500AI-ABZJ

Microchip Tech · USB Converters · QFN-56-EP(8x8)

LAN9500AI-ABZJ from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 nPHY_INT output In internal PHY mode it outputs the active-high internal PHY interrupt signal; in external PHY mode it is an active-low PHY interrupt input from the external PHY.
2 TXN bidirectional Ethernet TX data output negative, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled.
3 TXP bidirectional Ethernet TX data output positive, which may be swapped internally with the receive data inputs when Auto-MDIX is enabled.
4 VDD33A power_in +3.3V analog power supply; refer to the device reference schematics for connection information.
5 RXN bidirectional Ethernet RX data input negative, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled.
6 RXP bidirectional Ethernet RX data input positive, which may be swapped internally with the transmit data outputs when Auto-MDIX is enabled.
7 NC unconnected No-connect on LAN9500A/LAN9500Ai; the pin must be left floating for normal device operation.
8 EXRES passive External PHY bias resistor connection to ground; use 12.0K 1.0% for LAN9500A/LAN9500Ai.
9 VDD33A power_in +3.3V analog power supply; refer to the device reference schematics for connection information.
10 VDDPLL power_in Ethernet PLL power supply that must be connected to VDDCORE for proper operation.
11 USBDM bidirectional USB D- analog bidirectional signal whose function may be swapped with USBDP via the PORT_SWAP configuration strap.
12 USBDP bidirectional USB D+ analog bidirectional signal whose function may be swapped with USBDM via the PORT_SWAP configuration strap.
13 TEST2 passive Test pin that must always be connected to VSS for proper operation.
14 NC unconnected No-connect pin that must be left floating for normal device operation.
15 VDD33A power_in +3.3V analog power supply; refer to the device reference schematics for connection information.
16 USBRBIAS passive External USB bias resistor that sets HS transmit current and on-chip termination; connect to an external 12K 1.0% resistor to ground.
17 VDDUSBPLL power_in USB PLL supply that must be connected to VDDCORE for proper operation.
18 XI input External 25 MHz crystal input, which may also be driven by a single-ended clock oscillator with XO left unconnected.
19 XO output External 25 MHz crystal output that must be left unconnected when XI is driven by a single-ended clock oscillator.
20 VBUS_DET input 5V-tolerant input detecting upstream bus power that must be tied to VDD33IO for bus-powered applications; on LAN9500A/LAN9500Ai it may also signal bus power availability in PME mode.
21 VDDCORE power_out Digital core power supply output from the internal core regulator; refer to Section 4.0 for connection information.
22 MDC/GPIO2 bidirectional In internal PHY mode it is the PHY management clock or a programmable GPIO2 (push-pull, open-drain, or Schmitt input); in external PHY mode it outputs the management clock to the external PHY.
23 MDIO/GPIO1 bidirectional In external PHY mode it carries management data to/from the external PHY, while in internal PHY mode it is a programmable GPIO1; on LAN9500A/LAN9500Ai it may serve as the PME_MODE_SEL input.
24 nRESET input Active-low system reset input that allows external hardware to reset the device; on LAN9500A/LAN9500Ai it may signal PME_CLEAR when PME mode is in effect.
25 VDD33IO power_in +3.3V I/O power supply; refer to the device reference schematics for connection information.
26 nFDX_LED/GPIO8 bidirectional Open-drain Ethernet full-duplex indicator LED pin driven low (LED on) when the link operates in full-duplex mode, also usable as GPIO8 (12 mA sink open-drain).
27 nLNKA_LED/GPIO9 bidirectional Open-drain Ethernet link activity LED pin driven low (LED on) when a valid link is detected and pulsed for activity, also usable as GPIO9 (12 mA sink open-drain).
28 nSPD_LED/GPIO10 bidirectional Open-drain Ethernet speed indicator LED pin driven low (LED on) at 100 Mb/s or during auto-negotiation and high at 10 Mb/s, also usable as GPIO10.
29 EECLK/PWR_SEL output Drives the clock of the external EEPROM; the PWR_SEL configuration strap sets the default power mode (0 = bus powered, 1 = self powered) when no EEPROM is present.
30 EECS output Drives the chip select of the external EEPROM; an external pull-down is recommended because it may tri-state briefly during power-up.
31 EEDO/AUTOMDIX_EN output Drives the EEDI input of the external EEPROM; the AUTOMDIX_EN strap sets the default Auto-MDIX (0 = disabled, 1 = enabled).
32 EEDI input Input driven by the EEDO output of the external EEPROM.
33 TEST3 passive Test pin that must always be connected to VSS for proper operation.
34 PHY_SEL input Selects the internal Ethernet PHY (0) or the external PHY connected to the MII port (1).
35 VDD33IO power_in +3.3V I/O power supply; refer to the device reference schematics for connection information.
36 nTRST/RXD0 input Active-low JTAG test port reset input in internal PHY mode, or the receive data 0 input from the external PHY in external PHY mode.
37 TDO/nPHY_RST output JTAG test data output in internal PHY mode, or an active-low PHY reset output in external PHY mode.
38 TCK/RXD1 input JTAG test clock input with a maximum operating frequency of 25 MHz in internal PHY mode, or the receive data 1 input in external PHY mode.
39 TMS/RXD2 input JTAG test mode select input in internal PHY mode, or the receive data 2 input from the external PHY in external PHY mode.
40 TDI/RXD3 input JTAG test data input in internal PHY mode, or the receive data 3 input from the external PHY in external PHY mode.
41 RXCLK bidirectional Receive clock that is the receiver clock input from the external PHY in external PHY mode, or an MII signal visibility output in internal PHY mode.
42 RXDV bidirectional Receive data valid that is input from the external PHY in external PHY mode and indicates valid data on RXD[3:0].
43 TXEN bidirectional Transmit enable that is an output to the external PHY in external PHY mode and indicates valid data on TXD[3:0].
44 RXER bidirectional Receive error that is input from the external PHY in external PHY mode and indicates a receive error in the packet.
45 CRS/GPIO3 bidirectional Carrier sense that is input from the external PHY in external PHY mode and indicates a network carrier, or programmable GPIO3 in internal PHY mode.
46 COL/GPIO0 bidirectional MII collision detect input from the external PHY in external PHY mode, or programmable GPIO0 in internal PHY mode, which on LAN9500A/LAN9500Ai may signal PME.
47 TXCLK bidirectional Transmitter clock that is the transmitter clock input from the external PHY in external PHY mode.
48 VDD33IO power_in +3.3V I/O power supply; refer to the device reference schematics for connection information.
49 TEST1 passive Test pin that must always be connected to VDD33IO for proper operation.
50 VDDCORE power_out Digital core power supply output from the internal core regulator; refer to Section 4.0 for connection information.
51 VDD33IO power_in +3.3V I/O power supply; refer to the device reference schematics for connection information.
52 VDD33IO power_in +3.3V I/O power supply; refer to the device reference schematics for connection information.
53 TXD3/GPIO7/EEP_SIZE bidirectional Transmit data 3 output to the external PHY in external mode, or programmable GPIO7 in internal mode; the EEP_SIZE strap selects a 128-byte (0) or 256/512-byte (1) EEPROM.
54 TXD2/GPIO6/PORT_SWAP bidirectional Transmit data 2 output to the external PHY in external mode, or programmable GPIO6 in internal mode; the PORT_SWAP strap swaps the USBDP and USBDM mapping.
55 TXD1/GPIO5/RMT_WKP bidirectional Transmit data 1 output to the external PHY in external mode, or programmable GPIO5 in internal mode; the RMT_WKP strap enables (1) or disables (0) remote wakeup default descriptor values, overridden by the EEPROM.
56 TXD0/GPIO4/EEP_DISABLE bidirectional Transmit data 0 output to the external PHY in external mode, or programmable GPIO4 in internal mode; the EEP_DISABLE strap prevents EEPROM autoload when set to 1.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-56-EP(8x8)
Category Interface
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD33IO, VDD33A) absolute maximum 0 3.6 V Note 8-1 189
Positive voltage on signal pins, with respect to ground 6 V Note 8-2: does not apply to XI, XO, EXRES, USBRBIAS 189
Negative voltage on signal pins, with respect to ground -0.5 V Note 8-3: does not apply to EXRES, USBRBIAS 189
Positive voltage on XO, with respect to ground 2.5 V 189
Storage Temperature -55 150 °C 189
HBM ESD Performance -5 5 kV HBM; LAN9500A/LAN9500Ai (Note 8-6) 189
IEC61000-4-2 Contact Discharge ESD Performance -8 8 kV Note 8-7 189
IEC61000-4-2 Air-Gap Discharge ESD Performance -15 15 kV Note 8-7 189
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) tolerance -300 300 mV Around nominal +3.3V 189
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) nominal 3.3 V Operating conditions 189
Ambient Operating Temperature in Still Air (TA) TA -40 85 °C Industrial version (Note 8-5) 189
IS input low input level VILI -0.3 V IS Schmitt-triggered input 193
IS input high input level VIHI 3.6 V IS Schmitt-triggered input 193
IS negative-going threshold VILT 1.01 1.19 1.39 V Schmitt trigger 193
IS positive-going threshold VIHT 1.39 1.59 1.8 V Schmitt trigger 193
IS Schmitt trigger hysteresis (VIHT - VILT) VHYS 336 399 485 mV Schmitt trigger 193
IS input leakage IIH -10 10 µA VIN = VSS or VDD33IO 193
IS_5V input low input level VILI -0.3 V IS_5V 5V tolerant Schmitt-triggered input 193
IS_5V input high input level VIHI 5.5 V IS_5V 5V tolerant Schmitt-triggered input 193
IS_5V negative-going threshold VILT 1.01 1.19 1.39 V Schmitt trigger 193
IS_5V positive-going threshold VIHT 1.39 1.59 1.8 V Schmitt trigger 193
IS_5V Schmitt trigger hysteresis (VIHT - VILT) VHYS 336 399 485 mV Schmitt trigger 193
IS_5V input leakage IIH -10 10 µA VIN = VSS or VDD33IO 193
IS_5V input leakage at 5.5V IIH 79 µA VIN = 5.5V; Note 8-8, Note 8-9 (total 5.5V leakage for entire device) 193
O8 low output level VOL 0.4 V IOL = 8mA 193
OD8 low output level VOL 0.4 V IOL = 8mA 193
O12 low output level VOL 0.4 V IOL = 12mA 193
OD12 low output level VOL 0.4 V IOL = 12mA 193
ICLK (XI input) low input level VILI -0.3 0.5 V XI crystal oscillator input buffer 193
ICLK (XI input) high input level VIHI 0.8 V LAN9500A/LAN9500Ai (Note 8-11) 194
Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 8-12 194
Peak Differential Output Voltage Low VPPL -950 -1050 mVpk Note 8-12 194
Signal Amplitude Symmetry VSS 98 102 % Note 8-12 194
Signal Rise and Fall Time TRF 3 5 nS Note 8-12 194
Rise and Fall Symmetry TRFS 0.5 nS Note 8-12 194
Duty Cycle Distortion DCD 35 50 65 % Note 8-13 194
Overshoot and Undershoot VOS 5 % 194
Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 8-15 (100 Ω resistive load) 194
Receiver Differential Squelch Threshold VDS 300 420 585 mV 194
Crystal frequency tolerance @25°C (100 µW) Ftol -50 50 PPM Note 8-26; LAN9500A/LAN9500Ai only 206
Crystal frequency stability over temperature (100 µW) Ftemp -50 50 PPM Note 8-26; LAN9500A/LAN9500Ai only 205
Crystal total allowable PPM budget (100 µW) -50 50 PPM Note 8-28; IEEE 802.3u 205
Crystal shunt capacitance (100 µW) CO 5 pF LAN9500A/LAN9500Ai only 205
Crystal load capacitance (100 µW) CL 8 12 pF LAN9500A/LAN9500Ai only 205
Crystal equivalent series resistance (100 µW) R1 80 Ohm LAN9500A/LAN9500Ai only 205
XO series resistor (100 µW crystal circuit) Rs 495 500 505 Ohm LAN9500A/LAN9500Ai only 205
Crystal operating temperature range (100 µW) -40 85 °C Industrial version (Notes 8-30, 8-31); LAN9500A/LAN9500Ai only 205
Crystal drive level (300 µW) PW 300 µW 300 µW 25 MHz crystal 204
Crystal equivalent series resistance (300 µW) R1 50 Ohm 300 µW 25 MHz crystal 204
Crystal shunt capacitance (300 µW) CO 7 pF 300 µW 25 MHz crystal 204
Crystal load capacitance (300 µW) CL 20 pF 300 µW 25 MHz crystal 204
Crystal nominal frequency (25 MHz) Ffund 25 MHz Fundamental mode; 100 µW crystal table 205
XI pin capacitance 3 pF Note 8-32; includes pad, bond wire and lead frame 205
XO pin capacitance 3 pF Note 8-32; includes pad, bond wire and lead frame 205

CAD (KiCad official)

  • Symbol: LAN9500AI-ABZJ
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: lan9500ai-abzj-etched.step / lan9500ai-abzj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9500ai-abzj.step / lan9500ai-abzj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (214 pp, sha256 57c7730da3b38584, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF