LAN9354 from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OSCI	input	External 25 MHz crystal input, which can also be driven by a single-ended clock oscillator with OSCO left unconnected.
2	OSCO	output	External 25 MHz crystal output; leave unconnected when OSCI is driven by a single-ended clock oscillator.
3	OSCVDD12	power_in	Crystal +1.2 V power supply, supplied by the on-chip regulator unless regulator-off mode is configured via REG_EN.
4	OSCVSS	power_in	Crystal ground.
5	VDD33	power_in	+3.3 V power supply for the internal regulators, which must be supplied even if the internal regulators are disabled.
6	VDDCR	power_in	+1.2 V digital core supply, supplied by the on-chip regulator unless regulator-off mode is set via REG_EN; 1 µF and 470 pF decoupling capacitors in parallel to ground should be used on this pin.
7	REG_EN	passive	When tied to 3.3 V, the internal 1.2 V regulators are enabled.
8	FXLOSEN	input	Three-level strap selecting FX-LOS versus FX-SD/copper mode: below 1 V selects FX-SD/copper for both ports, 1.5 V selects FX-LOS for port A, and above 2 V selects FX-LOS for ports A and B.
9	FXSDA/FXLOSA/FXSDENA	input	Port A fiber signal detect input (valid above 2 V typ.) when FX-LOS mode is not selected, or fiber loss-of-signal input (high = LOS) in FX-LOS mode, with the FX-SD enable strap selecting FX-SD above 1 V (typ.).
10	FXSDB/FXLOSB/FXSDENB	input	Port B fiber signal detect input (valid above 2 V typ.) when FX-LOS mode is not selected, or fiber loss-of-signal input (high = LOS) in FX-LOS mode, with the FX-SD enable strap selecting FX-SD above 1 V (typ.).
11	RST#	input	Active-low system reset input with internal pull-up that may be left unconnected because an internal power-on reset exists, and must meet the reset timing requirements in Section 20.0.
12	GPIO7	bidirectional	General purpose I/O 7, fully programmable as a push-pull output, open-drain output, or Schmitt-triggered input via GPIO_CFG and GPIO_DATA_DIR.
13	GPIO6	bidirectional	General purpose I/O 6, fully programmable as a push-pull output, open-drain output, or Schmitt-triggered input via GPIO_CFG and GPIO_DATA_DIR.
14	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
15	LED5/GPIO5/PHYADD	bidirectional	LED 5 output when LED 5 Enable is set (open-drain polarity set by PHYADD strap at reset), otherwise GPIO5; the PHYADD strap sets the default Switch PHY Address Select soft-strap.
16	LED4/GPIO4/1588EN	bidirectional	LED 4 output when LED 4 Enable is set (open-drain polarity set by 1588EN strap at reset), otherwise GPIO4; the 1588EN strap sets the default 1588 Enable soft-strap.
17	P0_SPEED	input	In RMII MAC mode this live speed input is typically tied to the external PHY speed indication and can be overridden by VPHY_SPEED_SEL_LSB when auto-negotiation is cleared; it is not used in RMII PHY mode.
18	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
19	P0_OUTD1/P0_MODE2	bidirectional	Port 0 RMII output data bit 1 (8 mA drive; transmit data in MAC mode, receive data in PHY mode), also the Port 0 Mode[2] configuration strap.
20	P0_OUTD0/P0_MODE1	bidirectional	Port 0 RMII output data bit 0 (8 mA drive; transmit data in MAC mode, receive data in PHY mode), also the Port 0 Mode[1] configuration strap.
21	P0_OUTDV	output	RMII output data valid, which is TX_EN to the external PHY in MAC mode and CRS_DV to the external MAC in PHY mode (8 mA drive).
22	VDDCR	power_in	+1.2 V digital core supply, supplied by the on-chip regulator unless regulator-off mode is set via REG_EN.
23	P0_REFCLK/P0_MODE0	bidirectional	Port 0 RMII 50 MHz reference clock, an input or output selected by the RMII Clock Direction bit, with 12 mA or 16 mA drive when output; also the Port 0 Mode[0] configuration strap.
24	P0_INDV	input	RMII input data valid, which is CRS_DV from the external PHY in MAC mode and TX_EN from the external MAC in PHY mode (VIS input with pull-down).
25	P0_IND0	input	RMII input data bit 0, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode (VIS input with pull-down).
26	P0_IND1	input	RMII input data bit 1, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode (VIS input with pull-down).
27	RESERVED	unconnected	This pin is reserved and must be left unconnected for proper operation.
28	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
29	LED3/GPIO3/EEEEN	bidirectional	LED 3 output when LED 3 Enable is set (open-drain polarity set by EEEEN strap at reset), otherwise GPIO3; the EEEEN strap sets the default EEE Enable soft-straps.
30	P0_DUPLEX	input	In RMII MAC mode this live duplex input is typically tied to the external PHY duplex indication and can be overridden by VPHY_DUPLEX when auto-negotiation is cleared; it is not used in RMII PHY mode.
31	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
32	VDDCR	power_in	+1.2 V digital core supply, supplied by the on-chip regulator unless regulator-off mode is set via REG_EN.
33	P0_MDC	bidirectional	SMI/MII management clock: an input from an external master in slave modes and an output to external PHY(s) in MII master mode (8 mA); an external pull-down is recommended when SMI/MII is not used.
34	P0_MDIO	bidirectional	SMI/MII management data to/from an external master (slave modes) or external PHY(s) (MII master mode); an external pull-up is required when SMI or MII is used.
35	TESTMODE	input	This pin must be tied to VSS for proper operation.
36	I2CSDA/EESDA/TMS	bidirectional	I2C slave serial data input/output to/from the external master (VIS/VOD8), which must be pulled up by an external resistor at all times.
37	I2CSCL/EESCL/TCK	bidirectional	I2C slave serial clock input from the external master (VIS), which is not driven until the EEPROM is loaded.
38	IRQ	output	Interrupt request output whose polarity, source and buffer type (open-drain or push-pull) are programmable via the Interrupt Configuration Register (IRQ_CFG).
39	LED2/GPIO2/E2PSIZE	bidirectional	LED 2 output when LED 2 Enable is set (open-drain polarity set by E2PSIZE strap at reset), otherwise GPIO2; the E2PSIZE strap selects EEPROM size (low = 1K to 16K bits, high = 32K to 512K bits).
40	LED1/GPIO1/TDI	bidirectional	LED 1 output when LED 1 Enable is set, otherwise GPIO1 fully programmable as push-pull output, open-drain output, or Schmitt-triggered input.
41	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
42	LED0/GPIO0/TDO/MNGT0	bidirectional	LED 0 output when LED 0 Enable is set (open-drain polarity set by MNGT0 strap at reset), otherwise GPIO0; the MNGT0 strap selects serial management mode (0 = SMI, 1 = I2C).
43	VDD33TXRX1	power_in	+3.3 V Port A analog power supply (see power connection notes).
44	TXNA	bidirectional	Port A twisted pair transmit/receive negative channel 1 (AIO); in fiber mode this is the Port A FX transmit negative OLVPECL output.
45	TXPA	bidirectional	Port A twisted pair transmit/receive positive channel 1 (AIO); in fiber mode this is the Port A FX transmit positive OLVPECL output.
46	RXNA	bidirectional	Port A twisted pair transmit/receive negative channel 2 (AIO); in fiber mode this is the Port A FX receive negative analog input.
47	RXPA	bidirectional	Port A twisted pair transmit/receive positive channel 2 (AIO); in fiber mode this is the Port A FX receive positive analog input.
48	VDD12TX1	power_in	Port A transmitter +1.2 V supply from an external 1.2 V supply or the internal regulator; it must be tied to VDD12TX2 for proper operation.
49	RBIAS	passive	Bias reference for internal circuits, connected to an external 12.1 kΩ, 1% resistor to ground (nominal voltage 1.2 V).
50	VDD33BIAS	power_in	+3.3 V master bias power supply.
51	VDD12TX2	power_in	Port B transmitter +1.2 V supply from an external 1.2 V supply or the internal regulator; it must be tied to VDD12TX1 for proper operation.
52	RXPB	bidirectional	Port B twisted pair transmit/receive positive channel 2 (AIO); in fiber mode this is the Port B FX receive positive analog input.
53	RXNB	bidirectional	Port B twisted pair transmit/receive negative channel 2 (AIO); in fiber mode this is the Port B FX receive negative analog input.
54	TXPB	bidirectional	Port B twisted pair transmit/receive positive channel 1 (AIO); in fiber mode this is the Port B FX transmit positive OLVPECL output.
55	TXNB	bidirectional	Port B twisted pair transmit/receive negative channel 1 (AIO); in fiber mode this is the Port B FX transmit negative OLVPECL output.
56	VDD33TXRX2	power_in	+3.3 V Port B analog power supply (see power connection notes).
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Communication Interface Chip/UART/485/232
Pins	57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR)		0		1.5	V	Note 1	467
Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO)		0		3.6	V	Note 1	467
Ethernet Magnetics Supply Voltage		-0.5		3.6	V		467
Negative voltage on input signal pins, with respect to ground		-0.5			V	Note 3: does not apply to RBIAS	467
Positive voltage on OSCI, with respect to ground				3.6	V		467
Storage Temperature		-55		150	°C		467
Junction Temperature				150	°C		467
Low Input Level (IS type input buffer)	VILI	-0.3		0.8	V	Note 19: applies to all inputs and tri-stated bidirectional pins	472
High Input Level (IS type input buffer)	VIHI	2		3.6	V	Note 19	472
Input Leakage	IIH	-10		10	µA	VIN = VSS or VDD33	472
Low Input Level (FXSDENA/FXSDENB)	VIL	-0.3		0.8	V	AI type input buffer	472
High Input Level (FXSDENA/FXSDENB)	VIH	1.2			V	AI type input buffer; max printed as VDD33+0.3	472
State A Threshold (FXLOSEN Input)	VTHA	-0.3		0.8	V	AI type input buffer	472
State B Threshold (FXLOSEN Input)	VTHB	1.2		1.7	V	AI type input buffer	472
State C Threshold (FXLOSEN Input)	VTHC	2.3			V	AI type input buffer; max printed as VDD33+0.3	472
Low Input Level (OSCI Input)	VILI	-0.3		0.35	V	ICLK type input buffer; Note 20	472
High Input Level (OSCI Input)	VIHI			3.6	V	ICLK type input buffer; min printed as OSCVDD12-0.35	472
Input Leakage (OSCI Input)	IILCK	-10		10	µA	ICLK type input buffer	472
Low Output Level (VO8 type buffers)	VOL			0.4	V	IOL = 8 mA	474
Low Output Level (VOD8 type buffer)	VOL			0.4	V	IOL = 8 mA	474
Low Output Level (VO12 type buffers)	VOL			0.4	V	IOL = 12 mA	474
Low Output Level (VOD12 type buffer)	VOL			0.4	V	IOL = 12 mA	474
Low Output Level (VO16 type buffers)	VOL			0.4	V	IOL = 16 mA	474
Peak Differential Output Voltage High	VPPH	950		1050	mVpk	Note 24: measured at line side of transformer, line replaced by 100 Ω (±1%)	475
Peak Differential Output Voltage Low	VPPL	-950		-1050	mVpk	Note 24: measured at line side of transformer, line replaced by 100 Ω (±1%)	475
Signal Amplitude Symmetry	VSS	98		102	%	Note 24	475
Signal Rise and Fall Time	TRF	3		5	ns	Note 24	475
Rise and Fall Symmetry	TRFS			0.5	ns	Note 24	475
Duty Cycle Distortion	DCD	35	50	65	%	Note 25: offset from 16 ns pulse width at 50% of pulse peak	475
Overshoot and Undershoot	VOS			5	%		475
Jitter				1.4	ns	Note 26: measured differentially	475
Transmitter Peak Differential Output Voltage	VOUT	2.2	2.5	2.8	V	Note 27: min/max guaranteed with 100 Ω resistive load	475
Receiver Differential Squelch Threshold	VDS	300	420	585	mV		475
TCK clock period	ttckp	40			ns	Note: timing with respect to 25 pF test load; value placed in Min column by parameter meaning (single value in source)	466
TDI, TMS setup to TCK rising edge	tsu	5			ns	25 pF test load; placed in Min column by parameter meaning (single value in source)	466
TDI, TMS hold from TCK rising edge	th	5			ns	25 pF test load; placed in Min column by parameter meaning (single value in source)	466
TDO output valid from TCK falling edge	tdov			15	ns	25 pF test load; placed in Max column by parameter meaning (single value in source)	466
TDO output invalid from TCK falling edge	tdoinvld	0			ns	25 pF test load; placed in Min column by parameter meaning (single value in source)	466
Configuration strap valid time	tcfg			15	ms	Power-on configuration strap latching	479
OSCI Pin Capacitance			3		pF	Note 34: includes pad, bond wire and lead frame	480
OSCO Pin Capacitance			3		pF	Note 34: includes pad, bond wire and lead frame	480
Maximum Power (Internal Regulator Disabled, 2.5 V Ethernet Magnetics)				752	mW	Table 20-2	468
Maximum Power (Internal Regulator Disabled, 3.3 V Ethernet Magnetics)				927	mW	Table 20-2	468
Maximum Power (Internal Regulator Enabled, 2.5 V Ethernet Magnetics)				973	mW	Table 20-2	468
Maximum Power (Internal Regulator Enabled, 3.3 V Ethernet Magnetics)				1148	mW	Table 20-2	468
Thermal Resistance Junction to Ambient	JA		24.7		°C/W	Measured in still air (56-pin QFN)	468
Thermal Resistance Junction to Bottom of Case	JT		0.1		°C/W	Measured in still air (56-pin QFN)	468
Thermal Resistance Junction to Top of Case	JC		1.8		°C/W	Airflow 1 m/s (56-pin QFN)	468

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is	101

CAD (KiCad official)

Symbol: LAN9354
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
3D model files: lan9354-etched.step / lan9354-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9354.step / lan9354.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (487 pp, sha256 6d0f1e1a944406cb, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LAN9354

Verified LAN9354

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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