LAN9303M-AKZE

{
  "schema_version": 1,
  "type": "component",
  "slug": "lan9303m-akze",
  "title": "LAN9303M-AKZE",
  "brief": "Microchip Tech Ethernet ICs, QFN-72-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "communication interface chip-uart-485-232",
    "lan9303m-akze",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "LAN9303M-AKZE",
    "manufacturer": "Microchip Tech",
    "package": "QFN-72-EP(10x10)",
    "pin_count": 73,
    "category": "Communication Interface Chip/UART/485/232",
    "subcategory": "Ethernet ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/1b361d14bfdc8b5aa552835ddab338f0.pdf",
    "parts": {
      "symbol": "lan9303m-akze.kicad_sym",
      "footprint": "lan9303m-akze.kicad_mod",
      "model_3d": "lan9303m-akze-hero.glb",
      "model_3d_plain": "lan9303m-akze-etched.glb",
      "model_3d_step": "lan9303m-akze-etched.step",
      "model_3d_step_plain": "lan9303m-akze.step",
      "lbr": "lan9303m-akze.lbr"
    },
    "distributor_links": {
      "lcsc": "C633951",
      "digikey": "LAN9303M-AKZE-ND",
      "mouser": "886-LAN9303M-AKZE"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T16:26:08Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "LAN9303M-AKZE-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "886-LAN9303M-AKZE",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "P0_IND2",
        "type": "input",
        "description": "Port 0 MII input data bit 2, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "2",
        "name": "P0_IND1",
        "type": "input",
        "description": "Port 0 MII input data bit 1, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "3",
        "name": "P0_IND0",
        "type": "input",
        "description": "Port 0 MII input data bit 0, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "4",
        "name": "P0_INDV",
        "type": "input",
        "description": "Port 0 MII input data valid, RX_DV from the external PHY in MAC mode and TX_EN from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "5",
        "name": "P0_INER",
        "type": "input",
        "description": "Port 0 MII input error, RX_ER from the external PHY in MAC mode and TX_ER from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "6",
        "name": "P0_INCLK",
        "type": "bidirectional",
        "description": "Port 0 MII input reference clock, an input in MAC mode from the external PHY receive clock and a 12/16 mA output in PHY mode, with internal pull-down."
      },
      {
        "number": "7",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package."
      },
      {
        "number": "8",
        "name": "VDD18CORE",
        "type": "power_out",
        "description": "+1.8V digital core supply from the internal core voltage regulator; all VDD18CORE pins must be tied together."
      },
      {
        "number": "9",
        "name": "P0_OUTD3/DUPLEX_POL_0",
        "type": "output",
        "description": "Port 0 MII output data bit 3, an 8 mA output driving transmit data in MAC mode and receive data in PHY mode; DUPLEX_POL_0 is the duplex polarity strap, latched at reset."
      },
      {
        "number": "10",
        "name": "P0_OUTD2/P0_MODE2",
        "type": "output",
        "description": "Port 0 MII output data bit 2, an 8 mA output; P0_MODE2 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "11",
        "name": "P0_OUTD1/P0_MODE1",
        "type": "output",
        "description": "Port 0 MII output data bit 1, an 8 mA output; P0_MODE1 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "12",
        "name": "P0_OUTD0/P0_MODE0",
        "type": "output",
        "description": "Port 0 MII output data bit 0, an 8 mA output; P0_MODE0 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "13",
        "name": "P1_IND3",
        "type": "input",
        "description": "Port 1 MII input data bit 3, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "14",
        "name": "P1_IND2",
        "type": "input",
        "description": "Port 1 MII input data bit 2, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "15",
        "name": "P1_IND1",
        "type": "input",
        "description": "Port 1 MII input data bit 1, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "16",
        "name": "P1_IND0",
        "type": "input",
        "description": "Port 1 MII input data bit 0, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "17",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package."
      },
      {
        "number": "18",
        "name": "P1_INDV",
        "type": "input",
        "description": "Port 1 MII input data valid, RX_DV from the external PHY in MAC mode and TX_EN from the external MAC in PHY and RMII PHY modes, with internal pull-down."
      },
      {
        "number": "19",
        "name": "P1_INER",
        "type": "input",
        "description": "Port 1 MII input error, RX_ER from the external PHY in MAC mode and TX_ER from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "20",
        "name": "P1_INCLK",
        "type": "bidirectional",
        "description": "Port 1 MII input reference clock, an input in MAC mode from the external PHY receive clock and a 12/16 mA output in PHY mode, with internal pull-down."
      },
      {
        "number": "21",
        "name": "P0_OUTDV",
        "type": "output",
        "description": "Port 0 MII output data valid, TX_EN to the external PHY in MAC mode and RX_DV to the external MAC in PHY mode, an 8 mA output."
      },
      {
        "number": "22",
        "name": "P0_OUTCLK",
        "type": "bidirectional",
        "description": "Port 0 MII output reference clock, an input in MAC mode from the external PHY transmit clock and a 12/16 mA output in PHY mode, with internal pull-down."
      },
      {
        "number": "23",
        "name": "P0_COL",
        "type": "bidirectional",
        "description": "Port 0 MII collision, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-up."
      },
      {
        "number": "24",
        "name": "P0_CRS",
        "type": "bidirectional",
        "description": "Port 0 MII carrier sense, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "25",
        "name": "P0_DUPLEX",
        "type": "input",
        "description": "Port 0 MII duplex input, which can change at any time in MAC mode and sets the default duplex in PHY mode, with internal pull-up enabled."
      },
      {
        "number": "26",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Management data input/output, data to and from an external master in SMI/MII slave mode or from an external PHY in MII master mode; an external pull-up is required when SMI or MII is used."
      },
      {
        "number": "27",
        "name": "MDC",
        "type": "input",
        "description": "MII management clock, a clock input from an external master in SMI/MII slave mode and a clock output to an external PHY in MII master mode."
      },
      {
        "number": "28",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package."
      },
      {
        "number": "29",
        "name": "LED5/GPIO5/PHYADDR_LED5P",
        "type": "bidirectional",
        "description": "LED 5 output when enabled, otherwise GPIO5 with programmable push-pull, open-drain or Schmitt input; PHYADDR_LED5P is latched at reset to set PHY addresses and LED polarity."
      },
      {
        "number": "30",
        "name": "LED4/GPIO4/MNGT1_LED4P",
        "type": "bidirectional",
        "description": "LED 4 output when enabled, otherwise GPIO4 with programmable push-pull, open-drain or Schmitt input; MNGT1_LED4P is the serial management mode strap bit 1 and sets LED 4 polarity."
      },
      {
        "number": "31",
        "name": "LED3/GPIO3/MNGT0_LED3P",
        "type": "bidirectional",
        "description": "LED 3 output when enabled, otherwise GPIO3 with programmable push-pull, open-drain or Schmitt input; MNGT0_LED3P is the serial management mode strap bit 0 and sets LED 3 polarity."
      },
      {
        "number": "32",
        "name": "LED2/GPIO2/E2PSIZE_LED2P",
        "type": "bidirectional",
        "description": "LED 2 output when enabled, otherwise GPIO2 with programmable push-pull, open-drain or Schmitt input; E2PSIZE_LED2P sets the EEPROM size range and LED 2 polarity at reset."
      },
      {
        "number": "33",
        "name": "LED1/GPIO1/AMDIX2_LED1P",
        "type": "bidirectional",
        "description": "LED 1 output when enabled, otherwise GPIO1 with programmable push-pull, open-drain or Schmitt input; AMDIX2_LED1P sets the Port 2 Auto-MDIX default and LED 1 polarity at reset."
      },
      {
        "number": "34",
        "name": "LED0/GPIO0/AMDIX1_LED0P",
        "type": "bidirectional",
        "description": "LED 0 output when enabled, otherwise GPIO0 with programmable push-pull, open-drain or Schmitt input; AMDIX1_LED0P sets the Port 1 Auto-MDIX default and LED 0 polarity at reset."
      },
      {
        "number": "35",
        "name": "P1_DUPLEX",
        "type": "input",
        "description": "Port 1 MII duplex input, which can change at any time in MAC mode and sets the default duplex in PHY and RMII PHY modes, with internal pull-up enabled."
      },
      {
        "number": "36",
        "name": "P1_COL",
        "type": "bidirectional",
        "description": "Port 1 MII collision, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-up."
      },
      {
        "number": "37",
        "name": "P1_CRS",
        "type": "bidirectional",
        "description": "Port 1 MII carrier sense, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "38",
        "name": "P1_OUTD3/DUPLEX_POL_1",
        "type": "output",
        "description": "Port 1 MII output data bit 3, an 8 mA output driving transmit data in MAC mode and receive data in PHY mode; DUPLEX_POL_1 is the duplex polarity strap, latched at reset."
      },
      {
        "number": "39",
        "name": "P1_OUTD2/P1_MODE2",
        "type": "output",
        "description": "Port 1 MII output data bit 2, an 8 mA output; P1_MODE2 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "40",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package."
      },
      {
        "number": "41",
        "name": "VDD18CORE",
        "type": "power_out",
        "description": "+1.8V digital core supply from the internal core voltage regulator; all VDD18CORE pins must be tied together."
      },
      {
        "number": "42",
        "name": "P1_OUTDV",
        "type": "output",
        "description": "Port 1 MII output data valid, TX_EN to the external PHY in MAC mode and RX_DV to the external MAC in PHY mode, an 8 mA output."
      },
      {
        "number": "43",
        "name": "P1_OUTCLK",
        "type": "bidirectional",
        "description": "Port 1 MII output reference clock, an input in MAC mode from the external PHY transmit clock and a 12/16 mA output in PHY mode, with internal pull-down."
      },
      {
        "number": "44",
        "name": "P1_OUTD1/P1_MODE1",
        "type": "output",
        "description": "Port 1 MII output data bit 1, an 8 mA output; P1_MODE1 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "45",
        "name": "P1_OUTD0/P1_MODE0",
        "type": "output",
        "description": "Port 1 MII output data bit 0, an 8 mA output; P1_MODE0 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion."
      },
      {
        "number": "46",
        "name": "VDD33IO",
        "type": "power_in",
        "description": "+3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package."
      },
      {
        "number": "47",
        "name": "TEST1",
        "type": "input",
        "description": "Test pin that must be tied to VDD33IO for proper operation."
      },
      {
        "number": "48",
        "name": "TEST2",
        "type": "input",
        "description": "Test pin that must be tied to VSS for proper operation, with internal pull-down."
      },
      {
        "number": "49",
        "name": "EE_SDA/SDA",
        "type": "bidirectional",
        "description": "EEPROM I2C serial data input/output in EEPROM mode or I2C slave serial data in slave mode, requiring an external pull-up at all times."
      },
      {
        "number": "50",
        "name": "EE_SCL/SCL",
        "type": "bidirectional",
        "description": "EEPROM I2C serial clock input/open-drain output in EEPROM mode or I2C slave clock input in slave mode, requiring an external pull-up at all times."
      },
      {
        "number": "51",
        "name": "nRST",
        "type": "input",
        "description": "Active-low system reset input, internally pulled high, with timing requirements given in Section 14.5.2 and optional use when the internal power-on reset is sufficient."
      },
      {
        "number": "52",
        "name": "IRQ",
        "type": "output",
        "description": "Interrupt output whose polarity, source and buffer type (push-pull or open-drain) are set via the Interrupt Configuration Register."
      },
      {
        "number": "53",
        "name": "XI",
        "type": "input",
        "description": "External 25MHz crystal input, which can also be driven by a single-ended clock oscillator with XO left unconnected."
      },
      {
        "number": "54",
        "name": "XO",
        "type": "output",
        "description": "External 25MHz crystal output, left unconnected when XI is driven by a single-ended clock oscillator."
      },
      {
        "number": "55",
        "name": "VDD18PLL",
        "type": "power_in",
        "description": "PLL +1.8V power supply that must be connected to VDD18CORE for proper operation."
      },
      {
        "number": "56",
        "name": "TXN1",
        "type": "bidirectional",
        "description": "Port 1 Ethernet TX negative analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active."
      },
      {
        "number": "57",
        "name": "TXP1",
        "type": "bidirectional",
        "description": "Port 1 Ethernet TX positive analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active."
      },
      {
        "number": "58",
        "name": "VDD33A1",
        "type": "power_in",
        "description": "+3.3V Port 1 analog power supply."
      },
      {
        "number": "59",
        "name": "RXN1",
        "type": "bidirectional",
        "description": "Port 1 Ethernet RX negative analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active."
      },
      {
        "number": "60",
        "name": "RXP1",
        "type": "bidirectional",
        "description": "Port 1 Ethernet RX positive analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active."
      },
      {
        "number": "61",
        "name": "VDD33A1",
        "type": "power_in",
        "description": "+3.3V Port 1 analog power supply."
      },
      {
        "number": "62",
        "name": "VDD18TX1",
        "type": "power_in",
        "description": "Port 1 transmitter +1.8V supply that must be connected directly to VDD18TX2 for proper operation."
      },
      {
        "number": "63",
        "name": "EXRES",
        "type": "passive",
        "description": "Bias reference used for the internal bias circuits, connected to an external 12.4K ohm 1% resistor to ground."
      },
      {
        "number": "64",
        "name": "VDD33BIAS",
        "type": "power_in",
        "description": "+3.3V master bias power supply."
      },
      {
        "number": "65",
        "name": "VDD18TX2",
        "type": "power_in",
        "description": "Port 2 transmitter +1.8V supply from the internal PHY regulator that must be tied to VDD18TX1 for proper operation."
      },
      {
        "number": "66",
        "name": "VDD33A2",
        "type": "power_in",
        "description": "+3.3V Port 2 analog power supply."
      },
      {
        "number": "67",
        "name": "RXP2",
        "type": "bidirectional",
        "description": "Port 2 Ethernet RX positive analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active."
      },
      {
        "number": "68",
        "name": "RXN2",
        "type": "bidirectional",
        "description": "Port 2 Ethernet RX negative analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active."
      },
      {
        "number": "69",
        "name": "VDD33A2",
        "type": "power_in",
        "description": "+3.3V Port 2 analog power supply."
      },
      {
        "number": "70",
        "name": "TXP2",
        "type": "bidirectional",
        "description": "Port 2 Ethernet TX positive analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active."
      },
      {
        "number": "71",
        "name": "TXN2",
        "type": "bidirectional",
        "description": "Port 2 Ethernet TX negative analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active."
      },
      {
        "number": "72",
        "name": "P0_IND3",
        "type": "input",
        "description": "Port 0 MII input data bit 3, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down."
      },
      {
        "number": "73",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN suffix LAN9303M-AKZE is not stated in the excerpt. The datasheet covers LAN9303M and LAN9303; The exposed pad (VSS, must be connected to ground) is not numbered in Table 3-11 and is not listed a; Pins with multiple functions are listed under the primary name in Table 3-11. Types for dual-directi",
          "20/73 pins cited to the wrong page (name found elsewhere): ['9:P0_OUTD3/DUPLEX_POL_0@p22', '10:P0_OUTD2/P0_MODE2@p23', '11:P0_OUTD1/P0_MODE1@p23', '20:P1_INCLK@p17']"
        ],
        "pages_sent": 48,
        "cost_usd": 0.1008,
        "at": "2026-10-28T16:25:40"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/1b361d14bfdc8b5aa552835ddab338f0.pdf",
        "pages": 277,
        "sha256": "de1769f7f8714a48",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 73,
        "described": 73,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lan9303m-akze.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.02,
          10.02,
          0.9
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "6fb4bfb569031e2f96b6476780a7bb6b1e1c88d3ae11c06b98eeff4704884308",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lan9303m-akze-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.02,
          10.02,
          0.9
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "700c026c278f8a829fbd1e4c2dadf3d6307d7cf731ae2e0df0bf2fe586288b5e",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Microchip Tech",
      "Package": "QFN-72-EP(10x10)",
      "Category": "Communication Interface Chip/UART/485/232",
      "Pins": "73"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "de1769f7f8714a481c6d827604b03a2b60170e9cdd41e5bb08c1bbe7c3a6e253",
      "rows": [
        {
          "name": "Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)",
          "symbol": "",
          "kind": "absolute_maximum",
          "unit": "V",
          "min": 0,
          "typ": null,
          "max": 3.6,
          "conditions": "Note 14-1",
          "source_page": 251,
          "source": "datasheet"
        },
        {
          "name": "Positive voltage on signal pins, with respect to ground",
          "symbol": "",
          "kind": "absolute_maximum",
          "unit": "V",
          "min": null,
          "typ": null,
          "max": 6,
          "conditions": "Note 14-2; does not apply to XI, XO, EXRES",
          "source_page": 251,
          "source": "datasheet"
        },
        {
          "name": "Negative voltage on signal pins, with respect to ground",
          "symbol": "",
          "kind": "absolute_maximum",
          "unit": "V",
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