component
LAN9303M-AKZE
Public Made by Adomby adom
Microchip Tech Ethernet ICs, QFN-72-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLAN9303M-AKZE
Microchip Tech · Ethernet ICs · QFN-72-EP(10x10)
LAN9303M-AKZE from Microchip Tech, in a QFN-72-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0_IND2 | input | Port 0 MII input data bit 2, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down. |
| 2 | P0_IND1 | input | Port 0 MII input data bit 1, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 3 | P0_IND0 | input | Port 0 MII input data bit 0, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 4 | P0_INDV | input | Port 0 MII input data valid, RX_DV from the external PHY in MAC mode and TX_EN from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 5 | P0_INER | input | Port 0 MII input error, RX_ER from the external PHY in MAC mode and TX_ER from the external MAC in PHY mode, with internal pull-down. |
| 6 | P0_INCLK | bidirectional | Port 0 MII input reference clock, an input in MAC mode from the external PHY receive clock and a 12/16 mA output in PHY mode, with internal pull-down. |
| 7 | VDD33IO | power_in | +3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package. |
| 8 | VDD18CORE | power_out | +1.8V digital core supply from the internal core voltage regulator; all VDD18CORE pins must be tied together. |
| 9 | P0_OUTD3/DUPLEX_POL_0 | output | Port 0 MII output data bit 3, an 8 mA output driving transmit data in MAC mode and receive data in PHY mode; DUPLEX_POL_0 is the duplex polarity strap, latched at reset. |
| 10 | P0_OUTD2/P0_MODE2 | output | Port 0 MII output data bit 2, an 8 mA output; P0_MODE2 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 11 | P0_OUTD1/P0_MODE1 | output | Port 0 MII output data bit 1, an 8 mA output; P0_MODE1 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 12 | P0_OUTD0/P0_MODE0 | output | Port 0 MII output data bit 0, an 8 mA output; P0_MODE0 is the Port 0 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 13 | P1_IND3 | input | Port 1 MII input data bit 3, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down. |
| 14 | P1_IND2 | input | Port 1 MII input data bit 2, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down. |
| 15 | P1_IND1 | input | Port 1 MII input data bit 1, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 16 | P1_IND0 | input | Port 1 MII input data bit 0, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 17 | VDD33IO | power_in | +3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package. |
| 18 | P1_INDV | input | Port 1 MII input data valid, RX_DV from the external PHY in MAC mode and TX_EN from the external MAC in PHY and RMII PHY modes, with internal pull-down. |
| 19 | P1_INER | input | Port 1 MII input error, RX_ER from the external PHY in MAC mode and TX_ER from the external MAC in PHY mode, with internal pull-down. |
| 20 | P1_INCLK | bidirectional | Port 1 MII input reference clock, an input in MAC mode from the external PHY receive clock and a 12/16 mA output in PHY mode, with internal pull-down. |
| 21 | P0_OUTDV | output | Port 0 MII output data valid, TX_EN to the external PHY in MAC mode and RX_DV to the external MAC in PHY mode, an 8 mA output. |
| 22 | P0_OUTCLK | bidirectional | Port 0 MII output reference clock, an input in MAC mode from the external PHY transmit clock and a 12/16 mA output in PHY mode, with internal pull-down. |
| 23 | P0_COL | bidirectional | Port 0 MII collision, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-up. |
| 24 | P0_CRS | bidirectional | Port 0 MII carrier sense, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-down. |
| 25 | P0_DUPLEX | input | Port 0 MII duplex input, which can change at any time in MAC mode and sets the default duplex in PHY mode, with internal pull-up enabled. |
| 26 | MDIO | bidirectional | Management data input/output, data to and from an external master in SMI/MII slave mode or from an external PHY in MII master mode; an external pull-up is required when SMI or MII is used. |
| 27 | MDC | input | MII management clock, a clock input from an external master in SMI/MII slave mode and a clock output to an external PHY in MII master mode. |
| 28 | VDD33IO | power_in | +3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package. |
| 29 | LED5/GPIO5/PHYADDR_LED5P | bidirectional | LED 5 output when enabled, otherwise GPIO5 with programmable push-pull, open-drain or Schmitt input; PHYADDR_LED5P is latched at reset to set PHY addresses and LED polarity. |
| 30 | LED4/GPIO4/MNGT1_LED4P | bidirectional | LED 4 output when enabled, otherwise GPIO4 with programmable push-pull, open-drain or Schmitt input; MNGT1_LED4P is the serial management mode strap bit 1 and sets LED 4 polarity. |
| 31 | LED3/GPIO3/MNGT0_LED3P | bidirectional | LED 3 output when enabled, otherwise GPIO3 with programmable push-pull, open-drain or Schmitt input; MNGT0_LED3P is the serial management mode strap bit 0 and sets LED 3 polarity. |
| 32 | LED2/GPIO2/E2PSIZE_LED2P | bidirectional | LED 2 output when enabled, otherwise GPIO2 with programmable push-pull, open-drain or Schmitt input; E2PSIZE_LED2P sets the EEPROM size range and LED 2 polarity at reset. |
| 33 | LED1/GPIO1/AMDIX2_LED1P | bidirectional | LED 1 output when enabled, otherwise GPIO1 with programmable push-pull, open-drain or Schmitt input; AMDIX2_LED1P sets the Port 2 Auto-MDIX default and LED 1 polarity at reset. |
| 34 | LED0/GPIO0/AMDIX1_LED0P | bidirectional | LED 0 output when enabled, otherwise GPIO0 with programmable push-pull, open-drain or Schmitt input; AMDIX1_LED0P sets the Port 1 Auto-MDIX default and LED 0 polarity at reset. |
| 35 | P1_DUPLEX | input | Port 1 MII duplex input, which can change at any time in MAC mode and sets the default duplex in PHY and RMII PHY modes, with internal pull-up enabled. |
| 36 | P1_COL | bidirectional | Port 1 MII collision, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-up. |
| 37 | P1_CRS | bidirectional | Port 1 MII carrier sense, an input from the external PHY in MAC mode and an 8 mA output to the external MAC in PHY mode, with internal pull-down. |
| 38 | P1_OUTD3/DUPLEX_POL_1 | output | Port 1 MII output data bit 3, an 8 mA output driving transmit data in MAC mode and receive data in PHY mode; DUPLEX_POL_1 is the duplex polarity strap, latched at reset. |
| 39 | P1_OUTD2/P1_MODE2 | output | Port 1 MII output data bit 2, an 8 mA output; P1_MODE2 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 40 | VDD33IO | power_in | +3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package. |
| 41 | VDD18CORE | power_out | +1.8V digital core supply from the internal core voltage regulator; all VDD18CORE pins must be tied together. |
| 42 | P1_OUTDV | output | Port 1 MII output data valid, TX_EN to the external PHY in MAC mode and RX_DV to the external MAC in PHY mode, an 8 mA output. |
| 43 | P1_OUTCLK | bidirectional | Port 1 MII output reference clock, an input in MAC mode from the external PHY transmit clock and a 12/16 mA output in PHY mode, with internal pull-down. |
| 44 | P1_OUTD1/P1_MODE1 | output | Port 1 MII output data bit 1, an 8 mA output; P1_MODE1 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 45 | P1_OUTD0/P1_MODE0 | output | Port 1 MII output data bit 0, an 8 mA output; P1_MODE0 is the Port 1 mode configuration strap latched at power-on reset or nRST de-assertion. |
| 46 | VDD33IO | power_in | +3.3V power supply for I/O pins and the internal regulator; 5 such pins are on the package. |
| 47 | TEST1 | input | Test pin that must be tied to VDD33IO for proper operation. |
| 48 | TEST2 | input | Test pin that must be tied to VSS for proper operation, with internal pull-down. |
| 49 | EE_SDA/SDA | bidirectional | EEPROM I2C serial data input/output in EEPROM mode or I2C slave serial data in slave mode, requiring an external pull-up at all times. |
| 50 | EE_SCL/SCL | bidirectional | EEPROM I2C serial clock input/open-drain output in EEPROM mode or I2C slave clock input in slave mode, requiring an external pull-up at all times. |
| 51 | nRST | input | Active-low system reset input, internally pulled high, with timing requirements given in Section 14.5.2 and optional use when the internal power-on reset is sufficient. |
| 52 | IRQ | output | Interrupt output whose polarity, source and buffer type (push-pull or open-drain) are set via the Interrupt Configuration Register. |
| 53 | XI | input | External 25MHz crystal input, which can also be driven by a single-ended clock oscillator with XO left unconnected. |
| 54 | XO | output | External 25MHz crystal output, left unconnected when XI is driven by a single-ended clock oscillator. |
| 55 | VDD18PLL | power_in | PLL +1.8V power supply that must be connected to VDD18CORE for proper operation. |
| 56 | TXN1 | bidirectional | Port 1 Ethernet TX negative analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active. |
| 57 | TXP1 | bidirectional | Port 1 Ethernet TX positive analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active. |
| 58 | VDD33A1 | power_in | +3.3V Port 1 analog power supply. |
| 59 | RXN1 | bidirectional | Port 1 Ethernet RX negative analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active. |
| 60 | RXP1 | bidirectional | Port 1 Ethernet RX positive analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active. |
| 61 | VDD33A1 | power_in | +3.3V Port 1 analog power supply. |
| 62 | VDD18TX1 | power_in | Port 1 transmitter +1.8V supply that must be connected directly to VDD18TX2 for proper operation. |
| 63 | EXRES | passive | Bias reference used for the internal bias circuits, connected to an external 12.4K ohm 1% resistor to ground. |
| 64 | VDD33BIAS | power_in | +3.3V master bias power supply. |
| 65 | VDD18TX2 | power_in | Port 2 transmitter +1.8V supply from the internal PHY regulator that must be tied to VDD18TX1 for proper operation. |
| 66 | VDD33A2 | power_in | +3.3V Port 2 analog power supply. |
| 67 | RXP2 | bidirectional | Port 2 Ethernet RX positive analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active. |
| 68 | RXN2 | bidirectional | Port 2 Ethernet RX negative analog input of the 10/100 receiver, swapped with TX when HP Auto-MDIX is active. |
| 69 | VDD33A2 | power_in | +3.3V Port 2 analog power supply. |
| 70 | TXP2 | bidirectional | Port 2 Ethernet TX positive analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active. |
| 71 | TXN2 | bidirectional | Port 2 Ethernet TX negative analog output of the 10/100 transmitter, swapped with RX when HP Auto-MDIX is active. |
| 72 | P0_IND3 | input | Port 0 MII input data bit 3, receive data from the external PHY in MAC mode and transmit data from the external MAC in PHY mode, with internal pull-down. |
| 73 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-72-EP(10x10) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 73 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO) | 0 | 3.6 | V | Note 14-1 | 251 | ||
| Positive voltage on signal pins, with respect to ground | 6 | V | Note 14-2; does not apply to XI, XO, EXRES | 251 | |||
| Negative voltage on signal pins, with respect to ground | -0.5 | V | Note 14-3; does not apply to EXRES | 251 | |||
| Positive voltage on XI, with respect to ground | 4.6 | V | 251 | ||||
| Positive voltage on XO, with respect to ground | 2.5 | V | 251 | ||||
| Storage Temperature | -55 | 150 | oC | 251 | |||
| HBM ESD Performance | -8 | 8 | kV | per JESD 22-A114-E | 251 | ||
| Contact Discharge ESD Performance | -8 | 8 | kV | per IEC61000-4-2 (Note 14-5) | 251 | ||
| Air-Gap Discharge ESD Performance | -15 | 15 | kV | per IEC61000-4-2 (Note 14-5) | 251 | ||
| Latch-up Performance | -200 | 200 | mA | per EIA/JESD 78 | 251 | ||
| Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO) | 3 | 3.3 | 3.6 | V | +3.3V +/- 300mV | 251 | |
| Ambient Operating Temperature in Still Air (commercial version) | TA | 0 | 70 | oC | Note 14-4 commercial version | 251 | |
| Input Low Threshold (Negative-Going) | VILT | 1.01 | 1.18 | 1.35 | V | IS type Schmitt trigger input | 253 |
| Input High Threshold (Positive-Going) | VIHT | 1.39 | 1.6 | 1.8 | V | IS type Schmitt trigger input | 253 |
| Schmitt Trigger Hysteresis (VIHT - VILT) | VHYS | 345 | 420 | 485 | mV | Schmitt trigger | 253 |
| Input Leakage | IIN | -10 | 10 | uA | Note 14-6 | 253 | |
| Input Capacitance | CIN | 3 | pF | 253 | |||
| Low Input Level | VILI | -0.3 | V | IS type input buffer | 253 | ||
| High Input Level | VIHI | 3.6 | V | IS type input buffer | 253 | ||
| Low Output Level | VOL | 0.4 | V | O8 type buffer, IOL = 8mA | 253 | ||
| Low Input Level (XI input) | VILI | -0.3 | 0.5 | V | ICLK type buffer (XI input) | 253 | |
| High Input Level (XI input) | VIHI | 1.4 | 3.6 | V | ICLK type buffer (XI input) | 253 | |
| Supply current (10BASE-T full-duplex) @ 3.3V | 111 | mA | 10BASE-T full-duplex, 100% network loading | 251 | |||
| Supply current (100BASE-TX full-duplex) @ 3.3V | 190 | mA | 100BASE-TX full-duplex, 100% network loading | 252 | |||
| Peak Differential Output Voltage High | VPPH | 950 | 1050 | mVpk | Note 14-8 | 254 | |
| Peak Differential Output Voltage Low | VPPL | -950 | -1050 | mVpk | Note 14-8; values as printed | 254 | |
| Signal Amplitude Symmetry | VSS | 98 | 102 | % | Note 14-8 | 254 | |
| Signal Rise and Fall Time | TRF | 3 | 5 | nS | Note 14-8 | 254 | |
| Rise and Fall Symmetry | TRFS | 0.5 | nS | Note 14-8 | 254 | ||
| Duty Cycle Distortion | DCD | 35 | 50 | 65 | % | Note 14-9 | 254 |
| Overshoot and Undershoot | VOS | 5 | % | 254 | |||
| Jitter | 1.4 | nS | Note 14-10 measured differentially | 254 | |||
| Transmitter Peak Differential Output Voltage | VOUT | 2.2 | 2.5 | 2.8 | V | Note 14-11 | 254 |
| Receiver Differential Squelch Threshold | VDS | 300 | 420 | 585 | mV | 254 | |
| Input clock duty cycle | 40 | 50 | 60 | % | XI driven by single-ended clock oscillator | 269 | |
| Frequency Tolerance @ 25oC | Ftol | -50 | 50 | PPM | Note 14-22 | 269 | |
| Frequency Stability Over Temp | Ftemp | -50 | 50 | PPM | Note 14-22 | 269 | |
| Total Allowable PPM Budget | -50 | 50 | PPM | Note 14-24 | 269 | ||
| Drive Level | PW | 300 | uW | crystal | 269 | ||
| Equivalent Series Resistance | R1 | 30 | Ohm | crystal | 269 | ||
| Shunt Capacitance | CO | 7 | pF | crystal | 269 | ||
| Load Capacitance | CL | 20 | pF | crystal | 269 | ||
| Frequency | Ffund | 25 | MHz | fundamental mode | 269 | ||
| XI Pin Capacitance | 3 | pF | Note 14-27 | 269 | |||
| XO Pin Capacitance | 3 | pF | Note 14-27 | 269 |
CAD (KiCad official)
- Symbol:
LAN9303M-AKZE - Footprint:
Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm - 3D model: QFN-72-EP(10x10) (KiCad packages3D, STEP)
- 3D model files:
lan9303m-akze-etched.step/lan9303m-akze-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lan9303m-akze.step/lan9303m-akze.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (277 pp, sha256
de1769f7f8714a48, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).