LAN9252V

{
  "schema_version": 1,
  "type": "component",
  "slug": "lan9252v",
  "title": "LAN9252V",
  "brief": "Microchip Tech Interface - Specialized, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "communication interface chip-uart-485-232",
    "lan9252v",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "LAN9252V",
    "manufacturer": "Microchip Tech",
    "package": "QFN-64-EP(9x9)",
    "pin_count": 65,
    "category": "Communication Interface Chip/UART/485/232",
    "subcategory": "Interface - Specialized",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9454995c72fa47189fb93d7c94f5681b.pdf",
    "parts": {
      "symbol": "lan9252v.kicad_sym",
      "footprint": "lan9252v.kicad_mod",
      "model_3d": "lan9252v-hero.glb",
      "model_3d_plain": "lan9252v-etched.glb",
      "model_3d_step": "lan9252v-etched.step",
      "model_3d_step_plain": "lan9252v.step",
      "lbr": "lan9252v.lbr"
    },
    "distributor_links": {
      "lcsc": "C633499"
    },
    "distributor_check": {
      "checked_at": "2026-10-26T23:35:37Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "OSCI",
        "type": "input",
        "description": "External 25 MHz crystal input that can also be driven by a single-ended clock oscillator, in which case OSCO should be left unconnected."
      },
      {
        "number": "2",
        "name": "OSCO",
        "type": "output",
        "description": "External 25 MHz crystal output."
      },
      {
        "number": "3",
        "name": "OSCVDD12",
        "type": "power_in",
        "description": "Crystal +1.2 V power supply, supplied by the on-chip regulator unless configured for regulator off mode via REG_EN."
      },
      {
        "number": "4",
        "name": "OSCVSS",
        "type": "power_in",
        "description": "Crystal ground."
      },
      {
        "number": "5",
        "name": "VDD33",
        "type": "power_in",
        "description": "+3.3 V power supply for internal regulators, which must be supplied even if the internal regulators are disabled."
      },
      {
        "number": "6",
        "name": "VDDCR",
        "type": "power_in",
        "description": "+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN; 1 µF and 470 pF decoupling capacitors in parallel to ground should be used on this pin."
      },
      {
        "number": "7",
        "name": "REG_EN",
        "type": "input",
        "description": "When tied to 3.3 V, the internal 1.2 V regulators are enabled."
      },
      {
        "number": "8",
        "name": "FXLOSEN",
        "type": "input",
        "description": "Three-level strap that selects between FX-LOS and FX-SD / copper twisted pair mode for ports A and B."
      },
      {
        "number": "9",
        "name": "FXSDA/FXLOSA/FXSDENA",
        "type": "input",
        "description": "Port A fiber signal detect input, where a level above 2 V (typ.) indicates valid signal when FX-LOS mode is not selected."
      },
      {
        "number": "10",
        "name": "FXSDB/FXLOSB/FXSDENB",
        "type": "input",
        "description": "Port B fiber signal detect input, where a level above 2 V (typ.) indicates valid signal when FX-LOS mode is not selected."
      },
      {
        "number": "11",
        "name": "RST#",
        "type": "bidirectional",
        "description": "Active low system reset that is an input normally and an open-drain output during POR or EtherCAT reset; it may be left unconnected because an internal power-on reset is provided."
      },
      {
        "number": "12",
        "name": "D2",
        "type": "bidirectional",
        "description": "Host bus data bit 2 in non-multiplexed mode, shared with AD2, SOF and SIO2 in other modes."
      },
      {
        "number": "13",
        "name": "D1",
        "type": "bidirectional",
        "description": "Host bus data bit 1 in non-multiplexed mode, shared with AD1, EOF, SO and SIO1 in other modes."
      },
      {
        "number": "14",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.8 V to +3.3 V variable I/O power supply."
      },
      {
        "number": "15",
        "name": "D14",
        "type": "bidirectional",
        "description": "Host bus data bit 14 in non-multiplexed mode, shared with AD14, DIGIO8, GPI8/GPO8, MII_TXD3 and TX_SHIFT1 in other modes."
      },
      {
        "number": "16",
        "name": "D13",
        "type": "bidirectional",
        "description": "Host bus data bit 13 in non-multiplexed mode, shared with AD13, DIGIO7, GPI7/GPO7, MII_TXD2 and TX_SHIFT0 in other modes."
      },
      {
        "number": "17",
        "name": "D0",
        "type": "bidirectional",
        "description": "Host bus data bit 0 in non-multiplexed mode, shared with AD0, WD_STATE, SI and SIO0 in other modes."
      },
      {
        "number": "18",
        "name": "SYNC1/LATCH1",
        "type": "bidirectional",
        "description": "EtherCAT distributed clock Sync output or Latch input whose direction is bitwise configurable and which is not driven until the EEPROM is loaded."
      },
      {
        "number": "19",
        "name": "D9",
        "type": "bidirectional",
        "description": "Host bus data bit 9 in non-multiplexed mode, shared with AD9, LATCH_IN and SCK in other modes."
      },
      {
        "number": "20",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.8 V to +3.3 V variable I/O power supply."
      },
      {
        "number": "21",
        "name": "D12",
        "type": "bidirectional",
        "description": "Host bus data bit 12 in non-multiplexed mode, shared with AD12, DIGIO6, GPI6/GPO6 and MII_TXD1 in other modes."
      },
      {
        "number": "22",
        "name": "D11",
        "type": "bidirectional",
        "description": "Host bus data bit 11 in non-multiplexed mode, shared with AD11, DIGIO5, GPI5/GPO5 and MII_TXD0 in other modes."
      },
      {
        "number": "23",
        "name": "D10",
        "type": "bidirectional",
        "description": "Host bus data bit 10 in non-multiplexed mode, shared with AD10, DIGIO4, GPI4/GPO4 and MII_TXEN in other modes."
      },
      {
        "number": "24",
        "name": "VDDCR",
        "type": "power_in",
        "description": "+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN."
      },
      {
        "number": "25",
        "name": "A1",
        "type": "input",
        "description": "Host bus address bit 1 for non-multiplexed address mode, shared with ALELO, OE_EXT and MII_CLK25 in other modes."
      },
      {
        "number": "26",
        "name": "A3",
        "type": "input",
        "description": "Host bus address bit 3 for non-multiplexed address mode, shared with DIGIO11, GPI11/GPO11 and MII_RXDV in other modes."
      },
      {
        "number": "27",
        "name": "A4",
        "type": "input",
        "description": "Host bus address bit 4 for non-multiplexed address mode, shared with DIGIO12, GPI12/GPO12 and MII_RXD0 in other modes."
      },
      {
        "number": "28",
        "name": "CS",
        "type": "input",
        "description": "Host bus chip select, normally active low, indicating the device is selected for the current transfer."
      },
      {
        "number": "29",
        "name": "A2",
        "type": "input",
        "description": "Host bus address bit 2 for non-multiplexed address mode, shared with ALEHI, DIGIO10, GPI10/GPO10, LINKACTLED2 and MII_LINKPOL in other modes."
      },
      {
        "number": "30",
        "name": "WR/ENB",
        "type": "input",
        "description": "Host bus write strobe, normally active low, which in other configurations acts as the host bus enable strobe."
      },
      {
        "number": "31",
        "name": "RD/RD_WR",
        "type": "input",
        "description": "Host bus read strobe in one mode and direction control in conjunction with ENB, shared with DIGIO15, GPI15/GPO15 and MII_RXD3."
      },
      {
        "number": "32",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.8 V to +3.3 V variable I/O power supply."
      },
      {
        "number": "33",
        "name": "A0/D15",
        "type": "bidirectional",
        "description": "Host bus address bit 0 in non-multiplexed address mode and data bit 15 in 16-bit data mode, shared with AD15, DIGIO9, GPI9/GPO9 and MII_RXER."
      },
      {
        "number": "34",
        "name": "SYNC0/LATCH0",
        "type": "bidirectional",
        "description": "EtherCAT distributed clock Sync output or Latch input whose direction is bitwise configurable and which is not driven until the EEPROM is loaded."
      },
      {
        "number": "35",
        "name": "D3",
        "type": "bidirectional",
        "description": "Host bus data bit 3 in non-multiplexed mode, shared with AD3, WD_TRIG and SIO3 in other modes."
      },
      {
        "number": "36",
        "name": "D6",
        "type": "bidirectional",
        "description": "Host bus data bit 6 in non-multiplexed mode, shared with AD6, DIGIO0, GPI0/GPO0 and MII_RXCLK in other modes."
      },
      {
        "number": "37",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.8 V to +3.3 V variable I/O power supply."
      },
      {
        "number": "38",
        "name": "VDDCR",
        "type": "power_in",
        "description": "+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN."
      },
      {
        "number": "39",
        "name": "D7",
        "type": "bidirectional",
        "description": "Host bus data bit 7 in non-multiplexed mode, shared with AD7, DIGIO1, GPI1/GPO1 and MII_MDC in other modes."
      },
      {
        "number": "40",
        "name": "D8",
        "type": "bidirectional",
        "description": "Host bus data bit 8 in non-multiplexed mode, shared with AD8, DIGIO2, GPI2/GPO2 and MII_MDIO in other modes."
      },
      {
        "number": "41",
        "name": "TESTMODE",
        "type": "input",
        "description": "This pin must be tied to VSS for proper operation."
      },
      {
        "number": "42",
        "name": "EESDA/TMS",
        "type": "bidirectional",
        "description": "EEPROM I2C serial data input/open-drain output that must be pulled up by an external resistor at all times, shared with JTAG test mode select TMS."
      },
      {
        "number": "43",
        "name": "EESCL/TCK",
        "type": "bidirectional",
        "description": "EEPROM I2C clock open-drain output that must be pulled up by an external resistor at all times, shared with JTAG test clock TCK."
      },
      {
        "number": "44",
        "name": "IRQ",
        "type": "output",
        "description": "Interrupt request output whose polarity, source and buffer type are programmable via the Interrupt Configuration Register (IRQ_CFG)."
      },
      {
        "number": "45",
        "name": "RUNLED/E2PSIZE",
        "type": "output",
        "description": "Run LED output controlled by the AL Status Register, configured as open-drain or open-source depending on the strap sampled at reset."
      },
      {
        "number": "46",
        "name": "LINKACTLED1/TDI/CHIP_MODE1",
        "type": "output",
        "description": "Link/Activity LED output for port 1 (off = no link, on = link without activity, blinking = link and activity), shared with JTAG TDI and CHIP_MODE1."
      },
      {
        "number": "47",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.8 V to +3.3 V variable I/O power supply."
      },
      {
        "number": "48",
        "name": "LINKACTLED0/TDO/CHIP_MODE0",
        "type": "output",
        "description": "Link/Activity LED output for port 0 (off = no link, on = link without activity, blinking = link and activity), shared with JTAG TDO and CHIP_MODE0."
      },
      {
        "number": "49",
        "name": "D4",
        "type": "bidirectional",
        "description": "Host bus data bit 4 in non-multiplexed mode, shared with AD4, DIGIO3, GPI3/GPO3 and MII_LINK in other modes."
      },
      {
        "number": "50",
        "name": "D5",
        "type": "bidirectional",
        "description": "Host bus data bit 5 in non-multiplexed mode, shared with AD5, OUTVALID and SCS# in other modes."
      },
      {
        "number": "51",
        "name": "VDD33TXRX1",
        "type": "power_in",
        "description": "+3.3 V Port A analog power supply."
      },
      {
        "number": "52",
        "name": "TXNA",
        "type": "bidirectional",
        "description": "Port A twisted pair transmit/receive negative channel 1, which is also the Port A fiber transmit negative output."
      },
      {
        "number": "53",
        "name": "TXPA",
        "type": "bidirectional",
        "description": "Port A twisted pair transmit/receive positive channel 1, which is also the Port A fiber transmit positive output."
      },
      {
        "number": "54",
        "name": "RXNA",
        "type": "bidirectional",
        "description": "Port A twisted pair transmit/receive negative channel 2, which is also the Port A fiber receive negative input."
      },
      {
        "number": "55",
        "name": "RXPA",
        "type": "bidirectional",
        "description": "Port A twisted pair transmit/receive positive channel 2, which is also the Port A fiber receive positive input."
      },
      {
        "number": "56",
        "name": "VDD12TX1",
        "type": "power_in",
        "description": "Port A transmitter +1.2 V power supply that must be tied to the VDD12TX2 pin for proper operation."
      },
      {
        "number": "57",
        "name": "RBIAS",
        "type": "passive",
        "description": "Bias reference for internal bias circuits, which must be connected to an external 12.1 kΩ, 1% resistor to ground."
      },
      {
        "number": "58",
        "name": "VDD33BIAS",
        "type": "power_in",
        "description": "+3.3 V master bias power supply."
      },
      {
        "number": "59",
        "name": "VDD12TX2",
        "type": "power_in",
        "description": "Port B transmitter +1.2 V power supply that must be tied to the VDD12TX1 pin for proper operation."
      },
      {
        "number": "60",
        "name": "RXPB",
        "type": "bidirectional",
        "description": "Port B twisted pair transmit/receive positive channel 2, which is also the Port B fiber receive positive input."
      },
      {
        "number": "61",
        "name": "RXNB",
        "type": "bidirectional",
        "description": "Port B twisted pair transmit/receive negative channel 2, which is also the Port B fiber receive negative input."
      },
      {
        "number": "62",
        "name": "TXPB",
        "type": "bidirectional",
        "description": "Port B twisted pair transmit/receive positive channel 1, which is also the Port B fiber transmit positive output."
      },
      {
        "number": "63",
        "name": "TXNB",
        "type": "bidirectional",
        "description": "Port B twisted pair transmit/receive negative channel 1, which is also the Port B fiber transmit negative output."
      },
      {
        "number": "64",
        "name": "VDD33TXRX2",
        "type": "power_in",
        "description": "+3.3 V Port B analog power supply."
      },
      {
        "number": "65",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pages supplied do not include the ordering information that maps the LAN9252V suffix to a packag; The 9x9 mm body size is not stated in the supplied pages, so it could not be verified from the text.; The exposed pad is not a numbered pin in the datasheet; it is printed as 'Exposed Pad VSS' and is li"
        ],
        "pages_sent": 48,
        "cost_usd": 0.0865,
        "at": "2026-10-26T23:34:58"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/9454995c72fa47189fb93d7c94f5681b.pdf",
        "pages": 329,
        "sha256": "f9b73097c21a1ad5",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 65,
        "described": 65,
        "cites_pages": true,
        "refuses_to_fabricate": true
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        "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
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  },
  "metadata": {
    "specs": {
      "Manufacturer": "Microchip Tech",
      "Package": "QFN-64-EP(9x9)",
      "Category": "Communication Interface Chip/UART/485/232",
      "Pins": "65"
    },
    "appearance": {
      "contacts": {
        "quote": "with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is ",
        "page": 141,
        "doc": "ds.pdf",
        "material": "copper"
      },
      "version": 1,
      "datasheet_sha256": "f9b73097c21a1ad5e9b1a23ba10002c6bbeb7836422376c646e84313294e96c6"
    }
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  "author": {
    "name": "Ray",
    "email": "[email protected]"
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