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Contents

Pinout
Key specifications
Materials and finish
CAD (KiCad official)
Provenance

README

markdown

LAN9252V

Microchip Tech · Interface - Specialized · QFN-64-EP(9x9)

LAN9252V from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OSCI	input	External 25 MHz crystal input that can also be driven by a single-ended clock oscillator, in which case OSCO should be left unconnected.
2	OSCO	output	External 25 MHz crystal output.
3	OSCVDD12	power_in	Crystal +1.2 V power supply, supplied by the on-chip regulator unless configured for regulator off mode via REG_EN.
4	OSCVSS	power_in	Crystal ground.
5	VDD33	power_in	+3.3 V power supply for internal regulators, which must be supplied even if the internal regulators are disabled.
6	VDDCR	power_in	+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN; 1 µF and 470 pF decoupling capacitors in parallel to ground should be used on this pin.
7	REG_EN	input	When tied to 3.3 V, the internal 1.2 V regulators are enabled.
8	FXLOSEN	input	Three-level strap that selects between FX-LOS and FX-SD / copper twisted pair mode for ports A and B.
9	FXSDA/FXLOSA/FXSDENA	input	Port A fiber signal detect input, where a level above 2 V (typ.) indicates valid signal when FX-LOS mode is not selected.
10	FXSDB/FXLOSB/FXSDENB	input	Port B fiber signal detect input, where a level above 2 V (typ.) indicates valid signal when FX-LOS mode is not selected.
11	RST#	bidirectional	Active low system reset that is an input normally and an open-drain output during POR or EtherCAT reset; it may be left unconnected because an internal power-on reset is provided.
12	D2	bidirectional	Host bus data bit 2 in non-multiplexed mode, shared with AD2, SOF and SIO2 in other modes.
13	D1	bidirectional	Host bus data bit 1 in non-multiplexed mode, shared with AD1, EOF, SO and SIO1 in other modes.
14	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
15	D14	bidirectional	Host bus data bit 14 in non-multiplexed mode, shared with AD14, DIGIO8, GPI8/GPO8, MII_TXD3 and TX_SHIFT1 in other modes.
16	D13	bidirectional	Host bus data bit 13 in non-multiplexed mode, shared with AD13, DIGIO7, GPI7/GPO7, MII_TXD2 and TX_SHIFT0 in other modes.
17	D0	bidirectional	Host bus data bit 0 in non-multiplexed mode, shared with AD0, WD_STATE, SI and SIO0 in other modes.
18	SYNC1/LATCH1	bidirectional	EtherCAT distributed clock Sync output or Latch input whose direction is bitwise configurable and which is not driven until the EEPROM is loaded.
19	D9	bidirectional	Host bus data bit 9 in non-multiplexed mode, shared with AD9, LATCH_IN and SCK in other modes.
20	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
21	D12	bidirectional	Host bus data bit 12 in non-multiplexed mode, shared with AD12, DIGIO6, GPI6/GPO6 and MII_TXD1 in other modes.
22	D11	bidirectional	Host bus data bit 11 in non-multiplexed mode, shared with AD11, DIGIO5, GPI5/GPO5 and MII_TXD0 in other modes.
23	D10	bidirectional	Host bus data bit 10 in non-multiplexed mode, shared with AD10, DIGIO4, GPI4/GPO4 and MII_TXEN in other modes.
24	VDDCR	power_in	+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN.
25	A1	input	Host bus address bit 1 for non-multiplexed address mode, shared with ALELO, OE_EXT and MII_CLK25 in other modes.
26	A3	input	Host bus address bit 3 for non-multiplexed address mode, shared with DIGIO11, GPI11/GPO11 and MII_RXDV in other modes.
27	A4	input	Host bus address bit 4 for non-multiplexed address mode, shared with DIGIO12, GPI12/GPO12 and MII_RXD0 in other modes.
28	CS	input	Host bus chip select, normally active low, indicating the device is selected for the current transfer.
29	A2	input	Host bus address bit 2 for non-multiplexed address mode, shared with ALEHI, DIGIO10, GPI10/GPO10, LINKACTLED2 and MII_LINKPOL in other modes.
30	WR/ENB	input	Host bus write strobe, normally active low, which in other configurations acts as the host bus enable strobe.
31	RD/RD_WR	input	Host bus read strobe in one mode and direction control in conjunction with ENB, shared with DIGIO15, GPI15/GPO15 and MII_RXD3.
32	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
33	A0/D15	bidirectional	Host bus address bit 0 in non-multiplexed address mode and data bit 15 in 16-bit data mode, shared with AD15, DIGIO9, GPI9/GPO9 and MII_RXER.
34	SYNC0/LATCH0	bidirectional	EtherCAT distributed clock Sync output or Latch input whose direction is bitwise configurable and which is not driven until the EEPROM is loaded.
35	D3	bidirectional	Host bus data bit 3 in non-multiplexed mode, shared with AD3, WD_TRIG and SIO3 in other modes.
36	D6	bidirectional	Host bus data bit 6 in non-multiplexed mode, shared with AD6, DIGIO0, GPI0/GPO0 and MII_RXCLK in other modes.
37	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
38	VDDCR	power_in	+1.2 V digital core power supply, supplied by the on-chip regulator unless regulator off mode is set via REG_EN.
39	D7	bidirectional	Host bus data bit 7 in non-multiplexed mode, shared with AD7, DIGIO1, GPI1/GPO1 and MII_MDC in other modes.
40	D8	bidirectional	Host bus data bit 8 in non-multiplexed mode, shared with AD8, DIGIO2, GPI2/GPO2 and MII_MDIO in other modes.
41	TESTMODE	input	This pin must be tied to VSS for proper operation.
42	EESDA/TMS	bidirectional	EEPROM I2C serial data input/open-drain output that must be pulled up by an external resistor at all times, shared with JTAG test mode select TMS.
43	EESCL/TCK	bidirectional	EEPROM I2C clock open-drain output that must be pulled up by an external resistor at all times, shared with JTAG test clock TCK.
44	IRQ	output	Interrupt request output whose polarity, source and buffer type are programmable via the Interrupt Configuration Register (IRQ_CFG).
45	RUNLED/E2PSIZE	output	Run LED output controlled by the AL Status Register, configured as open-drain or open-source depending on the strap sampled at reset.
46	LINKACTLED1/TDI/CHIP_MODE1	output	Link/Activity LED output for port 1 (off = no link, on = link without activity, blinking = link and activity), shared with JTAG TDI and CHIP_MODE1.
47	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
48	LINKACTLED0/TDO/CHIP_MODE0	output	Link/Activity LED output for port 0 (off = no link, on = link without activity, blinking = link and activity), shared with JTAG TDO and CHIP_MODE0.
49	D4	bidirectional	Host bus data bit 4 in non-multiplexed mode, shared with AD4, DIGIO3, GPI3/GPO3 and MII_LINK in other modes.
50	D5	bidirectional	Host bus data bit 5 in non-multiplexed mode, shared with AD5, OUTVALID and SCS# in other modes.
51	VDD33TXRX1	power_in	+3.3 V Port A analog power supply.
52	TXNA	bidirectional	Port A twisted pair transmit/receive negative channel 1, which is also the Port A fiber transmit negative output.
53	TXPA	bidirectional	Port A twisted pair transmit/receive positive channel 1, which is also the Port A fiber transmit positive output.
54	RXNA	bidirectional	Port A twisted pair transmit/receive negative channel 2, which is also the Port A fiber receive negative input.
55	RXPA	bidirectional	Port A twisted pair transmit/receive positive channel 2, which is also the Port A fiber receive positive input.
56	VDD12TX1	power_in	Port A transmitter +1.2 V power supply that must be tied to the VDD12TX2 pin for proper operation.
57	RBIAS	passive	Bias reference for internal bias circuits, which must be connected to an external 12.1 kΩ, 1% resistor to ground.
58	VDD33BIAS	power_in	+3.3 V master bias power supply.
59	VDD12TX2	power_in	Port B transmitter +1.2 V power supply that must be tied to the VDD12TX1 pin for proper operation.
60	RXPB	bidirectional	Port B twisted pair transmit/receive positive channel 2, which is also the Port B fiber receive positive input.
61	RXNB	bidirectional	Port B twisted pair transmit/receive negative channel 2, which is also the Port B fiber receive negative input.
62	TXPB	bidirectional	Port B twisted pair transmit/receive positive channel 1, which is also the Port B fiber transmit positive output.
63	TXNB	bidirectional	Port B twisted pair transmit/receive negative channel 1, which is also the Port B fiber transmit negative output.
64	VDD33TXRX2	power_in	+3.3 V Port B analog power supply.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(9x9)
Category	Communication Interface Chip/UART/485/232
Pins	65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is	141

CAD (KiCad official)

Symbol: LAN9252V
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: lan9252v-etched.step / lan9252v-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9252v.step / lan9252v.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (329 pp, sha256 f9b73097c21a1ad5, retrieved 2026-10-26, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF