component
LAN8742A-CZ
Public Made by Adomby adom
Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "lan8742a-cz",
"version": "0.1.0",
"type": "component",
"description": "Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"interface",
"lan8742a-cz",
"factory-2.0.0",
"extractor-text"
],
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"component": {
"mpn": "LAN8742A-CZ",
"manufacturer": "Microchip Tech",
"package": "QFN-24-EP(4x4)",
"pin_count": 25,
"category": "Interface",
"subcategory": "Ethernet Transceivers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884593767931904",
"parts": {
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"model_3d_step_plain": "lan8742a-cz.step",
"lbr": "lan8742a-cz.lbr"
},
"distributor_links": {
"lcsc": "C220794",
"digikey": "LAN8742A-CZ-ND",
"mouser": "579-LAN8742A-CZ"
},
"distributor_check": {
"checked_at": "2026-10-21T00:04:16Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "LAN8742A-CZ-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "579-LAN8742A-CZ",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VDD2A",
"type": "power_in",
"description": "+3.3 V analog port power to Channel 2 and the internal regulator."
},
{
"number": "2",
"name": "LED2/nINT/nPME/nINTSEL",
"type": "bidirectional",
"description": "Multiplexed LED2 (Link Speed) output after reset, configurable as nINT or nPME, and the nINTSEL strap when pulled high at reset, which must be tied to VDD2A rather than VDDIO."
},
{
"number": "3",
"name": "LED1/nINT/nPME/REGOFF",
"type": "bidirectional",
"description": "Multiplexed LED1 (Link Activity) output after reset, configurable as nINT or nPME, and the REGOFF strap that disables the internal +1.2 V regulator when pulled high at reset, which must be tied to VDD2A rather than VDDIO."
},
{
"number": "4",
"name": "XTAL2",
"type": "output",
"description": "Crystal oscillator output (OCLK) for the 25 MHz crystal."
},
{
"number": "5",
"name": "XTAL1/CLKIN",
"type": "input",
"description": "Crystal oscillator input (ICLK) that also accepts an external reference clock, with the positive voltage limit relative to ground stated as +3.6 V."
},
{
"number": "6",
"name": "VDDCR",
"type": "power_in",
"description": "+1.2 V digital core supply, provided by the on-chip regulator unless REGOFF configures regulator-off mode, with 1 µF and 470 pF decoupling capacitors recommended to ground."
},
{
"number": "7",
"name": "RXD1/MODE1",
"type": "bidirectional",
"description": "Bit 1 of the 2-bit RMII receive data output (VO8, 8 mA sink and source), also sampled as the MODE1 configuration strap with internal pull-up."
},
{
"number": "8",
"name": "RXD0/MODE0",
"type": "bidirectional",
"description": "Bit 0 of the 2-bit RMII receive data output (VO8, 8 mA sink and source), also sampled as the MODE0 configuration strap with internal pull-up."
},
{
"number": "9",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power supply for the digital pins."
},
{
"number": "10",
"name": "RXER/PHYAD0",
"type": "bidirectional",
"description": "RMII receive error output (VO8) asserted when an error is detected in the frame being transferred, also sampled as the PHYAD0 strap (VIS, internal pull-down) that sets the SMI address."
},
{
"number": "11",
"name": "CRS_DV/MODE2",
"type": "bidirectional",
"description": "Multiplexed with the MODE2 configuration strap that, together with MODE0 and MODE1, sets the default PHY mode; the CRS_DV RMII function is described on page 12, which is not in the supplied excerpt."
},
{
"number": "12",
"name": "MDIO",
"type": "bidirectional",
"description": "SMI management data input/output with VIS/VO8 buffer type and internal pull-up, per the Rev 1.1 revision history."
},
{
"number": "13",
"name": "MDC",
"type": "input",
"description": "Serial Management Interface clock input; its full description is in Table 2.3 on page 15, which is not in the supplied excerpt."
},
{
"number": "14",
"name": "nINT/REFCLKO",
"type": "output",
"description": "Multiplexed nINT (interrupt) or REFCLKO (reference clock output) function selected by the nINTSEL strap; nINT is not available on this pin when REF_CLK is sourced from an external 25 MHz clock."
},
{
"number": "15",
"name": "nRST",
"type": "input",
"description": "Active-low hardware reset input; configuration straps are latched on power-on reset and on pin reset."
},
{
"number": "16",
"name": "TXEN",
"type": "input",
"description": "RMII transmit enable input (VIS with internal pull-down) indicating that valid transmit data is present on TXD[1:0]."
},
{
"number": "17",
"name": "TXD0",
"type": "input",
"description": "RMII transmit data bit 0 from the MAC, received on a variable-voltage Schmitt-triggered input (VIS)."
},
{
"number": "18",
"name": "TXD1",
"type": "input",
"description": "RMII transmit data bit 1 from the MAC, received on a variable-voltage Schmitt-triggered input (VIS)."
},
{
"number": "19",
"name": "VDD1A",
"type": "power_in",
"description": "+3.3 V analog port power to Channel 1."
},
{
"number": "20",
"name": "TXN",
"type": "passive",
"description": "Negative leg of the differential MDI transmit pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt."
},
{
"number": "21",
"name": "TXP",
"type": "passive",
"description": "Positive leg of the differential MDI transmit pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt."
},
{
"number": "22",
"name": "RXN",
"type": "passive",
"description": "Negative leg of the differential MDI receive pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt."
},
{
"number": "23",
"name": "RXP",
"type": "passive",
"description": "Positive leg of the differential MDI receive pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt."
},
{
"number": "24",
"name": "RBIAS",
"type": "passive",
"description": "Connects the external bias reference resistor to the central bias circuit; its value is specified in Table 2.6 on page 16, which is not in the supplied excerpt."
},
{
"number": "25",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pages 12 to 16 (rest of Table 2.1, Tables 2.2 to 2.6) are not in the supplied excerpt. Descriptions ; The exposed pad (VSS) is not numbered on the package, so it is not listed as a pin. The datasheet sa; Multiplexed pins are assigned a single KiCad type, but the datasheet gives a different buffer per fu",
"3/25 pins cited to the wrong page (name found elsewhere): ['4:XTAL2@p19', '11:CRS_DV/MODE2@p36', '15:nRST@p35']"
],
"pages_sent": 24,
"cost_usd": 0.1558,
"at": "2026-10-21T00:00:39"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884593767931904",
"pages": 132,
"sha256": "7f3c0c1f27c20293",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 25,
"described": 25,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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"sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",
"checked": "2026-10-21",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "lan8742a-cz-etched.step",
"role": "eda",
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