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LAN8742A-CZ

Microchip Tech · Ethernet Transceivers · QFN-24-EP(4x4)

LAN8742A-CZ from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD2A	power_in	+3.3 V analog port power to Channel 2 and the internal regulator.
2	LED2/nINT/nPME/nINTSEL	bidirectional	Multiplexed LED2 (Link Speed) output after reset, configurable as nINT or nPME, and the nINTSEL strap when pulled high at reset, which must be tied to VDD2A rather than VDDIO.
3	LED1/nINT/nPME/REGOFF	bidirectional	Multiplexed LED1 (Link Activity) output after reset, configurable as nINT or nPME, and the REGOFF strap that disables the internal +1.2 V regulator when pulled high at reset, which must be tied to VDD2A rather than VDDIO.
4	XTAL2	output	Crystal oscillator output (OCLK) for the 25 MHz crystal.
5	XTAL1/CLKIN	input	Crystal oscillator input (ICLK) that also accepts an external reference clock, with the positive voltage limit relative to ground stated as +3.6 V.
6	VDDCR	power_in	+1.2 V digital core supply, provided by the on-chip regulator unless REGOFF configures regulator-off mode, with 1 µF and 470 pF decoupling capacitors recommended to ground.
7	RXD1/MODE1	bidirectional	Bit 1 of the 2-bit RMII receive data output (VO8, 8 mA sink and source), also sampled as the MODE1 configuration strap with internal pull-up.
8	RXD0/MODE0	bidirectional	Bit 0 of the 2-bit RMII receive data output (VO8, 8 mA sink and source), also sampled as the MODE0 configuration strap with internal pull-up.
9	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply for the digital pins.
10	RXER/PHYAD0	bidirectional	RMII receive error output (VO8) asserted when an error is detected in the frame being transferred, also sampled as the PHYAD0 strap (VIS, internal pull-down) that sets the SMI address.
11	CRS_DV/MODE2	bidirectional	Multiplexed with the MODE2 configuration strap that, together with MODE0 and MODE1, sets the default PHY mode; the CRS_DV RMII function is described on page 12, which is not in the supplied excerpt.
12	MDIO	bidirectional	SMI management data input/output with VIS/VO8 buffer type and internal pull-up, per the Rev 1.1 revision history.
13	MDC	input	Serial Management Interface clock input; its full description is in Table 2.3 on page 15, which is not in the supplied excerpt.
14	nINT/REFCLKO	output	Multiplexed nINT (interrupt) or REFCLKO (reference clock output) function selected by the nINTSEL strap; nINT is not available on this pin when REF_CLK is sourced from an external 25 MHz clock.
15	nRST	input	Active-low hardware reset input; configuration straps are latched on power-on reset and on pin reset.
16	TXEN	input	RMII transmit enable input (VIS with internal pull-down) indicating that valid transmit data is present on TXD[1:0].
17	TXD0	input	RMII transmit data bit 0 from the MAC, received on a variable-voltage Schmitt-triggered input (VIS).
18	TXD1	input	RMII transmit data bit 1 from the MAC, received on a variable-voltage Schmitt-triggered input (VIS).
19	VDD1A	power_in	+3.3 V analog port power to Channel 1.
20	TXN	passive	Negative leg of the differential MDI transmit pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt.
21	TXP	passive	Positive leg of the differential MDI transmit pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt.
22	RXN	passive	Negative leg of the differential MDI receive pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt.
23	RXP	passive	Positive leg of the differential MDI receive pair that connects through the magnetics to the RJ45; its electrical limits are in Table 2.4 on page 15, which is not in the supplied excerpt.
24	RBIAS	passive	Connects the external bias reference resistor to the central bias circuit; its value is specified in Table 2.6 on page 16, which is not in the supplied excerpt.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-24-EP(4x4)
Category	Interface
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDDIO, VDD1A, VDD2A)		-0.5		3.6	V		113
Digital Core Supply Voltage (VDDCR)		-0.5		1.5	V		113
Ethernet Magnetics Supply Voltage		-0.5		3.6	V		113
Negative voltage on input signal pins, with respect to ground		-0.5			V	Note 5.3: does not apply to RBIAS	113
Positive voltage on XTAL1/CLKIN, with respect to ground				3.6	V		113
Storage Temperature		-55		150	°C		113
Supply Voltage (VDDIO)	VDDIO	1.62		3.6	V		114
Analog Port Supply Voltage (VDD1A, VDD2A)	VDD1A, VDD2A	3		3.6	V		114
Digital Core Supply Voltage (VDDCR)	VDDCR	1.14		1.26	V		114
Ethernet Magnetics Supply Voltage		2.25		3.6	V		114
Ambient Operating Temperature in Still Air (TA)	TA	0		70	°C	Commercial version (Note 5.4)	114
Thermal Resistance	ΘJA		55.3		°C/W	Measured in still air from the die to ambient air; multi-layer 2S2P PCB per JESD51	114
Junction-to-Top-of-Package	ΨJT		0.9		°C/W	Measured in still air	114
Schmitt Trigger Hysteresis (VIHT - VILT), IS type input buffer	VHYS	336	399	459	mV	Schmitt trigger	117
Input Leakage, IS type input buffer	IIH	-10		10	µA	VIN = VSS or VDDIO	117
Low Output Level, O12 buffer	VOL			0.4	V	IOL = 12 mA	117
Low Input Level, ICLK buffer (XTAL1)	VILI	-0.3		0.35	V		117
High Input Level, ICLK buffer (XTAL1)	VIHI			3.6	V		117
Input Leakage, VIS type variable voltage input buffer	IIH	-10		10	µA	VIN = VSS or VDDIO	118
Low Input Level, VIS type variable voltage input buffer	VILI	-0.3			V		118
High Input Level, VIS type variable voltage input buffer	VIHI			3.6	V		118
Low Output Level, VO8 buffer	VOL			0.4	V	IOL = 8 mA	118
Low Output Level, VOD8 buffer	VOL			0.4	V	IOL = 8 mA	118
Peak Differential Output Voltage High	VPPH	950		1050	mVpk	Measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	118
Peak Differential Output Voltage Low	VPPL	-950		-1050	mVpk	Measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	118
Signal Amplitude Symmetry	VSS	98		102	%	Measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	118
Signal Rise and Fall Time	TRF	3		5	ns	Measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	118
Rise and Fall Symmetry	TRFS			0.5	ns	Measured at line side of transformer, line replaced by 100 Ω (±1%) resistor	118
Duty Cycle Distortion	DCD	35	50	65	%	Offset from 16 ns pulse width at 50% of pulse peak	118
Overshoot and Undershoot	VOS			5	%		118
Transmitter Peak Differential Output Voltage	VOUT	2.2	2.5	2.8	V	Min/max guaranteed as measured with 100 Ω resistive load	119
Receiver Differential Squelch Threshold	VDS	300	420	585	mV		119
Power supply turn on time	tpon			50	ms		120
Power supply turn off time	tpoff			500	ms		120
MDC period	tclkp	400			ns		126
MDC high time	tclkh	160			ns		126
MDC low time	tclkl	160			ns		126
MDIO (read from PHY) output valid from rising edge of MDC	tval			300	ns		126
MDIO (read from PHY) output invalid from rising edge of MDC	toinvld	0			ns		126
MDIO (write to PHY) setup time to rising edge of MDC	tsu	10			ns		126
MDIO (write to PHY) input hold time after rising edge of MDC	tihold	10			ns		126
Frequency Tolerance at 25°C	Ftol	-50		50	ppm	At 25°C (Note 5.15)	127
Frequency Stability Over Temp	Ftemp	-50		50	ppm	Note 5.15	127
Total Allowable PPM Budget		-50		50	ppm	Note 5.17 (IEEE 802.3u)	127
Drive Level	PW	300			µW		127
Equivalent Series Resistance	R1			30	Ω		127
Operating Temperature Range (crystal)		0		70	°C	Commercial version (Notes 5.18, 5.19)	127

CAD (KiCad official)

Symbol: LAN8742A-CZ
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: lan8742a-cz-etched.step / lan8742a-cz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8742a-cz.step / lan8742a-cz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (132 pp, sha256 7f3c0c1f27c20293, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF