LAN8720AI-CP

{
  "slug": "lan8720ai-cp",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "lan8720ai-cp",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lan8720ai-cp.kicad_sym",
    "lan8720ai-cp.kicad_mod",
    "lan8720ai-cp.glb",
    "lan8720ai-cp.step",
    "lan8720ai-cp.lbr",
    "docs/hero.png",
    "docs/lan8720ai-cp-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lan8720ai-cp-hero.glb",
    "lan8720ai-cp-hero.overlay.json",
    "lan8720ai-cp-etched.glb"
  ],
  "component": {
    "mpn": "LAN8720AI-CP",
    "manufacturer": "Microchip Tech",
    "package": "QFN-24-EP(4x4)",
    "pin_count": 25,
    "category": "Interface",
    "subcategory": "Ethernet Transceivers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893401127665664",
    "parts": {
      "symbol": "lan8720ai-cp.kicad_sym",
      "footprint": "lan8720ai-cp.kicad_mod",
      "model_3d": "lan8720ai-cp-hero.glb",
      "model_3d_plain": "lan8720ai-cp-etched.glb",
      "model_3d_step": "lan8720ai-cp-etched.step",
      "model_3d_step_plain": "lan8720ai-cp.step",
      "lbr": "lan8720ai-cp.lbr"
    },
    "distributor_links": {
      "lcsc": "C633282"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T11:32:04Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD2A",
        "type": "power_in",
        "description": "+3.3V analog port power to Channel 2 and the internal regulator."
      },
      {
        "number": "2",
        "name": "LED2/nINTSEL",
        "type": "bidirectional",
        "description": "Link speed LED output (O12) that is active at 100Mbps, also the nINTSEL strap (internal pull-up) that selects nINT (floated or high to VDD2A) or REFCLKO (low to VSS) on pin 14."
      },
      {
        "number": "3",
        "name": "LED1/REGOFF",
        "type": "bidirectional",
        "description": "Link activity LED output (O12) that is active on valid link and blinks on activity, also the REGOFF strap (internal pull-down) where pulling high to VDD2A disables the internal 1.2V regulator."
      },
      {
        "number": "4",
        "name": "XTAL2",
        "type": "output",
        "description": "External crystal output; leave unconnected when a single-ended clock oscillator drives XTAL1/CLKIN."
      },
      {
        "number": "5",
        "name": "XTAL1/CLKIN",
        "type": "input",
        "description": "External crystal input or single-ended clock oscillator input (50MHz REF_CLK in REF_CLK In mode)."
      },
      {
        "number": "6",
        "name": "VDDCR",
        "type": "power_in",
        "description": "+1.2V digital core power supplied by the on-chip regulator unless REGOFF disables it, with 1uF and 470pF decoupling capacitors in parallel to ground."
      },
      {
        "number": "7",
        "name": "RXD1/MODE1",
        "type": "bidirectional",
        "description": "Receive data bit 1 output (VO8) that doubles as the MODE1 configuration strap (internal pull-up) setting the default PHY mode."
      },
      {
        "number": "8",
        "name": "RXD0/MODE0",
        "type": "bidirectional",
        "description": "Receive data bit 0 output (VO8) that doubles as the MODE0 configuration strap (internal pull-up) setting the default PHY mode."
      },
      {
        "number": "9",
        "name": "VDDIO",
        "type": "power_in",
        "description": "+1.6V to +3.6V variable I/O power."
      },
      {
        "number": "10",
        "name": "RXER/PHYAD0",
        "type": "bidirectional",
        "description": "Receive error output (VO8) that doubles as the PHYAD0 strap (internal pull-down) setting the SMI address to 0 or 1."
      },
      {
        "number": "11",
        "name": "CRS_DV/MODE2",
        "type": "bidirectional",
        "description": "Carrier sense/receive data valid output (VO8) that doubles as the MODE2 configuration strap (internal pull-up) setting the default PHY mode."
      },
      {
        "number": "12",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Serial Management Interface data input/output (VIS/VOD8)."
      },
      {
        "number": "13",
        "name": "MDC",
        "type": "input",
        "description": "Serial Management Interface clock input (VIS)."
      },
      {
        "number": "14",
        "name": "nINT/REFCLKO",
        "type": "output",
        "description": "Active-low open-drain interrupt output (VOD8, internal pull-up, add external pull-up to VDDIO) or optional 50MHz reference clock output (VO8), selected by the nINTSEL strap."
      },
      {
        "number": "15",
        "name": "nRST",
        "type": "input",
        "description": "Active-low system reset input (VIS, internal pull-up)."
      },
      {
        "number": "16",
        "name": "TXEN",
        "type": "input",
        "description": "Transmit enable input (VIS, internal pull-down) indicating valid transmission data is present on TXD[1:0]."
      },
      {
        "number": "17",
        "name": "TXD0",
        "type": "input",
        "description": "Transmit data bit 0 input (VIS) from the MAC."
      },
      {
        "number": "18",
        "name": "TXD1",
        "type": "input",
        "description": "Transmit data bit 1 input (VIS) from the MAC."
      },
      {
        "number": "19",
        "name": "VDD1A",
        "type": "power_in",
        "description": "+3.3V analog port power to Channel 1."
      },
      {
        "number": "20",
        "name": "TXN",
        "type": "bidirectional",
        "description": "Ethernet transmit/receive negative channel 1 (analog bidirectional)."
      },
      {
        "number": "21",
        "name": "TXP",
        "type": "bidirectional",
        "description": "Ethernet transmit/receive positive channel 1 (analog bidirectional)."
      },
      {
        "number": "22",
        "name": "RXN",
        "type": "bidirectional",
        "description": "Ethernet transmit/receive negative channel 2 (analog bidirectional)."
      },
      {
        "number": "23",
        "name": "RXP",
        "type": "bidirectional",
        "description": "Ethernet transmit/receive positive channel 2 (analog bidirectional)."
      },
      {
        "number": "24",
        "name": "RBIAS",
        "type": "passive",
        "description": "Analog reference input requiring a 12.1k ohm (1%) resistor to ground, nominal 1.2V and about 1mW dissipation."
      },
      {
        "number": "25",
        "name": "VSS",
        "type": "power_in",
        "description": "Exposed pad common ground, which must be connected to the ground plane with a via array."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed pad (VSS, ground) on the bottom of the package must be connected to ground, per Figure 2; These pins are multiplexed with configuration straps (nINTSEL, REGOFF, MODE[2:0], PHYAD0). Each is l; VDDCR is supplied by the internal regulator by default but becomes an external 1.2V input in regulat",
          "exposed pad 25 added from the footprint",
          "6/25 pins cited to the wrong page (name found elsewhere): ['4:XTAL2@p10', '13:MDC@p9', '16:TXEN@p7', '17:TXD0@p7']"
        ],
        "pages_sent": 22,
        "cost_usd": 0.1075,
        "at": "2026-10-18T11:30:14"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893401127665664",
        "pages": 78,
        "sha256": "fe56a1de03873781",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 25,
        "described": 25,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lan8720ai-cp.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lan8720ai-cp-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8d03f8066198af55e1347e822b9dacdd331405434b6ebc01fab818547bb8ca09",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}