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LAN8720AI-CP

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Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LAN8720AI-CP

Microchip Tech · Ethernet Transceivers · QFN-24-EP(4x4)

LAN8720AI-CP from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD2A power_in +3.3V analog port power to Channel 2 and the internal regulator.
2 LED2/nINTSEL bidirectional Link speed LED output (O12) that is active at 100Mbps, also the nINTSEL strap (internal pull-up) that selects nINT (floated or high to VDD2A) or REFCLKO (low to VSS) on pin 14.
3 LED1/REGOFF bidirectional Link activity LED output (O12) that is active on valid link and blinks on activity, also the REGOFF strap (internal pull-down) where pulling high to VDD2A disables the internal 1.2V regulator.
4 XTAL2 output External crystal output; leave unconnected when a single-ended clock oscillator drives XTAL1/CLKIN.
5 XTAL1/CLKIN input External crystal input or single-ended clock oscillator input (50MHz REF_CLK in REF_CLK In mode).
6 VDDCR power_in +1.2V digital core power supplied by the on-chip regulator unless REGOFF disables it, with 1uF and 470pF decoupling capacitors in parallel to ground.
7 RXD1/MODE1 bidirectional Receive data bit 1 output (VO8) that doubles as the MODE1 configuration strap (internal pull-up) setting the default PHY mode.
8 RXD0/MODE0 bidirectional Receive data bit 0 output (VO8) that doubles as the MODE0 configuration strap (internal pull-up) setting the default PHY mode.
9 VDDIO power_in +1.6V to +3.6V variable I/O power.
10 RXER/PHYAD0 bidirectional Receive error output (VO8) that doubles as the PHYAD0 strap (internal pull-down) setting the SMI address to 0 or 1.
11 CRS_DV/MODE2 bidirectional Carrier sense/receive data valid output (VO8) that doubles as the MODE2 configuration strap (internal pull-up) setting the default PHY mode.
12 MDIO bidirectional Serial Management Interface data input/output (VIS/VOD8).
13 MDC input Serial Management Interface clock input (VIS).
14 nINT/REFCLKO output Active-low open-drain interrupt output (VOD8, internal pull-up, add external pull-up to VDDIO) or optional 50MHz reference clock output (VO8), selected by the nINTSEL strap.
15 nRST input Active-low system reset input (VIS, internal pull-up).
16 TXEN input Transmit enable input (VIS, internal pull-down) indicating valid transmission data is present on TXD[1:0].
17 TXD0 input Transmit data bit 0 input (VIS) from the MAC.
18 TXD1 input Transmit data bit 1 input (VIS) from the MAC.
19 VDD1A power_in +3.3V analog port power to Channel 1.
20 TXN bidirectional Ethernet transmit/receive negative channel 1 (analog bidirectional).
21 TXP bidirectional Ethernet transmit/receive positive channel 1 (analog bidirectional).
22 RXN bidirectional Ethernet transmit/receive negative channel 2 (analog bidirectional).
23 RXP bidirectional Ethernet transmit/receive positive channel 2 (analog bidirectional).
24 RBIAS passive Analog reference input requiring a 12.1k ohm (1%) resistor to ground, nominal 1.2V and about 1mW dissipation.
25 VSS power_in Exposed pad common ground, which must be connected to the ground plane with a via array.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-24-EP(4x4)
Category Interface
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDIO) - variable I/O VDDIO 1.62 3.6 V After power-up, must hold +/-10% 52
Analog Port Supply Voltage VDD1A, VDD2A 3 3.6 V 52
Digital Core Supply Voltage VDDCR 1.08 1.32 V 52
Ethernet Magnetics Supply Voltage 2.25 3.6 V 52
Ambient Operating Temperature in Still Air TA -40 85 °C Industrial version (Note 5-4) 52
Supply Voltage (VDDIO, VDD1A, VDD2A) VDDIO, VDD1A, VDD2A -0.5 3.6 V Note 5-1 52
Digital Core Supply Voltage VDDCR -0.5 1.5 V Note 5-1 52
Ethernet Magnetics Supply Voltage -0.5 3.6 V 52
Positive voltage on signal pins, with respect to ground 6 V Note 5-2; does not apply to XTAL1/CLKIN, XTAL2, RBIAS 52
Negative voltage on signal pins, with respect to ground -0.5 V Note 5-3; does not apply to RBIAS 52
Positive voltage on XTAL1/CLKIN, with respect to ground XTAL1/CLKIN 3.6 V 52
Positive voltage on XTAL2, with respect to ground XTAL2 2.5 V 52
Storage Temperature -55 150 °C 52
IEC61000-4-2 Contact Discharge ESD Performance -8 8 kV Note 5-5 (independent 3rd party test) 52
IEC61000-4-2 Air-Gap Discharge ESD Performance -15 15 kV Note 5-5 (independent 3rd party test) 52
Latch-up Performance -150 150 mA per EIA/JESD 78 52
IIH Input Leakage IIH -10 10 uA VIN = VSS or VDDIO 55
ICLK Type Buffer (XTAL1 Input) Low Input Level VILI -0.3 0.35 V Note 5-10 55
ICLK Type Buffer (XTAL1 Input) High Input Level VIHI 0.9 3.6 V Note 5-10 55
O12 Type Buffers Low Output Level VOL 0.4 V IOL = 12mA 55
VO8 Type Buffers Low Output Level VOL 0.4 V IOL = 8mA 56
VOD8 Type Buffer Low Output Level VOL 0.4 V IOL = 8mA 56
Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 5-12 56
Peak Differential Output Voltage Low VPPL -950 -1050 mVpk Note 5-12 (min/max as printed) 56
Signal Amplitude Symmetry VSS 98 102 % Note 5-12 56
Signal Rise and Fall Time TRF 3 5 nS Note 5-12 56
Rise and Fall Symmetry TRFS 0.5 nS Note 5-12 56
Duty Cycle Distortion DCD 35 50 65 % Note 5-13 56
Overshoot and Undershoot VOS 5 % 56
Jitter (100BASE-TX) 1.4 nS Note 5-14 56
Transmitter Peak Differential Output Voltage (10BASE-T) VOUT 2.2 2.5 2.8 V Note 5-15: measured at line side of transformer, line replaced by 100 ohm resistor 57
Receiver Differential Squelch Threshold (10BASE-T) VDS 300 420 585 mV 57
Power supply turn on time tpon 50 mS 58
Power supply turn off time tpoff 500 mS 58
Total Current, REF_CLK IN mode, 100BASE-TX w/ traffic 49 mA Max row; Note 5-8 (VDDIO=1.8V & internal regulator disabled) 53
Total Current, REF_CLK IN mode, 10BASE-T w/ traffic 24 mA Max row; Note 5-8 (VDDIO=1.8V & internal regulator disabled) 53
Total Current, REF_CLK IN mode, Energy Detect Power Down 7.4 mA Max row; Note 5-8 (VDDIO=1.8V & internal regulator disabled) 53
Total Current, REF_CLK IN mode, General Power Down 3.4 mA Max row; Note 5-8 (VDDIO=1.8V & internal regulator disabled) 53
Total Current, REF_CLK OUT mode, 100BASE-T w/ traffic 54 mA Max row; Note 5-11 (VDDIO=1.8V & internal regulator disabled) 54
Total Current, REF_CLK OUT mode, 10BASE-T w/ traffic 30 mA Max row; Note 5-11 (VDDIO=1.8V & internal regulator disabled) 54
Total Current, REF_CLK OUT mode, Energy Detect Power Down 7.5 mA Max row; Note 5-11 (VDDIO=1.8V & internal regulator disabled) 54
Total Current, REF_CLK OUT mode, General Power Down 3.1 mA Max row; Note 5-11 (VDDIO=1.8V & internal regulator disabled) 54
RMII CLKIN (REF_CLK) frequency 50 MHz 62
RMII CLKIN Frequency Drift -50 50 ppm Printed as +/-50 ppm 62
RMII CLKIN Duty Cycle 40 60 % 62
RMII CLKIN Jitter 150 psec p-p not RMS 62
MDC period tclkp 400 ns 62
MDC high time tclkh 160 ns Printed as 160 (80%) 62
MDC low time tclkl 160 ns Printed as 160 (80%) 62
MDIO (read from PHY) output valid from rising edge of MDC tval 300 ns 62
MDIO (read from PHY) output hold from rising edge of MDC tohold 0 ns 62
MDIO (write to PHY) setup time to rising edge of MDC tsu 10 ns 62
MDIO (write to PHY) input hold time after rising edge of MDC tihold 10 ns 62
XTAL2 Series Resistor (100uW 25MHz crystal circuit) Rs 495 500 505 Ohm 65

CAD (KiCad official)

  • Symbol: LAN8720AI-CP
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lan8720ai-cp-etched.step / lan8720ai-cp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8720ai-cp.step / lan8720ai-cp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (78 pp, sha256 fe56a1de03873781, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF