LAN7430

{
  "slug": "lan7430",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Interface - Specialized, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "communication interface chip-uart-485-232",
    "lan7430",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lan7430.kicad_sym",
    "lan7430.kicad_mod",
    "lan7430.glb",
    "lan7430.step",
    "lan7430.lbr",
    "docs/hero.png",
    "docs/lan7430-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lan7430-hero.glb",
    "lan7430-hero.overlay.json",
    "lan7430-etched.glb"
  ],
  "component": {
    "mpn": "LAN7430",
    "manufacturer": "Microchip Tech",
    "package": "QFN-48-EP(7x7)",
    "pin_count": 49,
    "category": "Communication Interface Chip/UART/485/232",
    "subcategory": "Interface - Specialized",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/3aae0fa39559c93683db0bdc8262e5dd.pdf",
    "parts": {
      "symbol": "lan7430.kicad_sym",
      "footprint": "lan7430.kicad_mod",
      "model_3d": "lan7430-hero.glb",
      "model_3d_plain": "lan7430-etched.glb",
      "model_3d_step": "lan7430-etched.step",
      "model_3d_step_plain": "lan7430.step",
      "lbr": "lan7430.lbr"
    },
    "distributor_links": {
      "lcsc": "C633486"
    },
    "distributor_check": {
      "checked_at": "2026-10-27T06:49:05Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AVDDH_1",
        "type": "power_in",
        "description": "2.5V or 3.3V power for analog IO; on the LAN7430 it powers the Gigabit PHY transmitter, bandgap reference, and crystal oscillator amplifier."
      },
      {
        "number": "2",
        "name": "TXRXP_A",
        "type": "bidirectional",
        "description": "Media Dependent Interface[0] positive signal of the differential pair for Gigabit Ethernet channel A."
      },
      {
        "number": "3",
        "name": "TXRXM_A",
        "type": "bidirectional",
        "description": "Media Dependent Interface[0] negative signal of the differential pair for Gigabit Ethernet channel A."
      },
      {
        "number": "4",
        "name": "AVDDL_1",
        "type": "power_in",
        "description": "1.2V power for the analog core of the Ethernet PHY."
      },
      {
        "number": "5",
        "name": "TXRXP_B",
        "type": "bidirectional",
        "description": "Media Dependent Interface[1] positive signal of the differential pair for Gigabit Ethernet channel B."
      },
      {
        "number": "6",
        "name": "TXRXM_B",
        "type": "bidirectional",
        "description": "Media Dependent Interface[1] negative signal of the differential pair for Gigabit Ethernet channel B."
      },
      {
        "number": "7",
        "name": "TXRXP_C",
        "type": "bidirectional",
        "description": "Media Dependent Interface[2] positive signal of the differential pair for Gigabit Ethernet channel C; not used in 10BT/100BT mode."
      },
      {
        "number": "8",
        "name": "TXRXM_C",
        "type": "bidirectional",
        "description": "Media Dependent Interface[2] negative signal of the differential pair for Gigabit Ethernet channel C; not used in 10BT/100BT mode."
      },
      {
        "number": "9",
        "name": "AVDDL_2",
        "type": "power_in",
        "description": "Additional 1.2V power pin for the analog core (LAN7430 only)."
      },
      {
        "number": "10",
        "name": "TXRXP_D",
        "type": "bidirectional",
        "description": "Media Dependent Interface[3] positive signal of the differential pair for Gigabit Ethernet channel D; not used in 10BT/100BT mode."
      },
      {
        "number": "11",
        "name": "TXRXM_D",
        "type": "bidirectional",
        "description": "Media Dependent Interface[3] negative signal of the differential pair for Gigabit Ethernet channel D; not used in 10BT/100BT mode."
      },
      {
        "number": "12",
        "name": "AVDDH_2",
        "type": "power_in",
        "description": "2.5V or 3.3V power for analog IO; on the LAN7430 it provides power for the Gigabit PHY transmitter."
      },
      {
        "number": "13",
        "name": "VDD12CORE",
        "type": "power_in",
        "description": "1.2V digital core power supply input."
      },
      {
        "number": "14",
        "name": "VP",
        "type": "power_in",
        "description": "1.2V PCIe PHY analog and digital power."
      },
      {
        "number": "15",
        "name": "GD_1",
        "type": "power_in",
        "description": "PCIe ground."
      },
      {
        "number": "16",
        "name": "PCIE_RX_P",
        "type": "input",
        "description": "PCIe serial data input positive, a differential input link running at 2.5 GT/s."
      },
      {
        "number": "17",
        "name": "PCIE_RX_M",
        "type": "input",
        "description": "PCIe serial data input negative, a differential input link running at 2.5 GT/s."
      },
      {
        "number": "18",
        "name": "GD_2",
        "type": "power_in",
        "description": "PCIe ground."
      },
      {
        "number": "19",
        "name": "PCIE_TX_P",
        "type": "output",
        "description": "PCIe serial data output positive, a differential output link running at 2.5 GT/s; a series capacitor of 100nF to 200nF is required."
      },
      {
        "number": "20",
        "name": "VPTX",
        "type": "power_in",
        "description": "1.2V PCIe PHY transmit power."
      },
      {
        "number": "21",
        "name": "PCIE_TX_M",
        "type": "output",
        "description": "PCIe serial data output negative, a differential output link running at 2.5 GT/s; a series capacitor of 100nF to 200nF is required."
      },
      {
        "number": "22",
        "name": "GD_3",
        "type": "power_in",
        "description": "PCIe ground."
      },
      {
        "number": "23",
        "name": "VPH",
        "type": "power_in",
        "description": "2.5V PCIe PHY high voltage power."
      },
      {
        "number": "24",
        "name": "RESREF",
        "type": "input",
        "description": "External reference resistor pin that must be connected to ground through a 200 ohm 1% 100 ppm/C resistor."
      },
      {
        "number": "25",
        "name": "PCIE_CLK_P",
        "type": "input",
        "description": "PCIe differential reference clock input positive, which receives a 100 MHz differential clock."
      },
      {
        "number": "26",
        "name": "PCIE_CLK_M",
        "type": "input",
        "description": "PCIe differential reference clock input negative, which receives a 100 MHz differential clock."
      },
      {
        "number": "27",
        "name": "VDD25_REG_OUT",
        "type": "power_out",
        "description": "2.5V output from the integrated LDO, used to power the PCIe PHY and optionally the Gigabit Ethernet PHY AFE; the LDO requires a 1.0 uF 0.1-ohm ESR capacitor on this pin."
      },
      {
        "number": "28",
        "name": "VDD_REG_IN",
        "type": "power_in",
        "description": "3.3V input supply to the integrated LDO; if set to 2.5V it must be externally connected to VDD25_REG_OUT."
      },
      {
        "number": "29",
        "name": "RESET_N",
        "type": "input",
        "description": "System reset input that is active low; if unused it must be pulled up to VDDVARIO."
      },
      {
        "number": "30",
        "name": "TEST",
        "type": "input",
        "description": "Test mode enable pin that must be connected to ground for proper functional operation."
      },
      {
        "number": "31",
        "name": "VDD12CORE",
        "type": "power_in",
        "description": "1.2V digital core power supply input."
      },
      {
        "number": "32",
        "name": "VDD12_SW_OUT",
        "type": "power_out",
        "description": "1.2V unfiltered output voltage from the integrated switching regulator, which requires an external LC filter."
      },
      {
        "number": "33",
        "name": "VDD_SW_IN",
        "type": "power_in",
        "description": "1.8V to 3.3V input voltage for the integrated switching regulator."
      },
      {
        "number": "34",
        "name": "VDD12_SW_FB",
        "type": "power_in",
        "description": "Feedback pin for the integrated switching regulator; tie to VDD_SW_IN to disable the regulator."
      },
      {
        "number": "35",
        "name": "VAUX_DET/GPIO3/LED3/TCK",
        "type": "bidirectional",
        "description": "Auxiliary voltage detect input that indicates PME from D3cold support when tied to 3.3V, and is not supported when tied to VSS; it is multiplexed with GPIO3, LED3, and TCK."
      },
      {
        "number": "36",
        "name": "EECLK/GPIO2/LED2/TMS/ADV_PM_DISABLE",
        "type": "bidirectional",
        "description": "EEPROM clock output that drives the external EEPROM clock input; it is multiplexed with GPIO2, LED2, TMS, and the ADV_PM_DISABLE configuration strap."
      },
      {
        "number": "37",
        "name": "EEDIO/GPIO1/LED1/TDO",
        "type": "bidirectional",
        "description": "Bidirectional EEPROM data pin that requires an external resistor on the EEPROM data output to prevent read contention; it is multiplexed with GPIO1, LED1, and TDO."
      },
      {
        "number": "38",
        "name": "EECS/GPIO0/LED0/TDI",
        "type": "bidirectional",
        "description": "EEPROM chip select output that drives the external EEPROM chip select input; it is multiplexed with GPIO0, LED0, and TDI."
      },
      {
        "number": "39",
        "name": "VDDVARIO",
        "type": "power_in",
        "description": "1.8V to 3.3V variable supply for the I/Os."
      },
      {
        "number": "40",
        "name": "VDD12CORE",
        "type": "power_in",
        "description": "1.2V digital core power supply input."
      },
      {
        "number": "41",
        "name": "VDD_OTP",
        "type": "power_in",
        "description": "3.3V supply to the OTP charge pump."
      },
      {
        "number": "42",
        "name": "CLKREQ#",
        "type": "bidirectional",
        "description": "Open-drain clock request signal used to power manage the link clock and for L1 substate control."
      },
      {
        "number": "43",
        "name": "WAKE#",
        "type": "bidirectional",
        "description": "PCIe wake signal that is driven low when the device detects a wakeup; it is isolated from the PCIe bus when the device is powered down."
      },
      {
        "number": "44",
        "name": "PERST#",
        "type": "input",
        "description": "PCIe reset input indicating that both PCIe power and clock are available."
      },
      {
        "number": "45",
        "name": "AVDD12",
        "type": "power_in",
        "description": "1.2V power supply for the PLL and DLL."
      },
      {
        "number": "46",
        "name": "XO",
        "type": "output",
        "description": "Crystal output that connects to one lead of a 25MHz crystal; it is not connected when an oscillator or external clock is used."
      },
      {
        "number": "47",
        "name": "XI",
        "type": "input",
        "description": "Crystal input that connects to a 25MHz crystal or receives a 3.3V oscillator or external reference clock with ±50ppm tolerance."
      },
      {
        "number": "48",
        "name": "ISET",
        "type": "input",
        "description": "External PHY bias resistor pin that must be connected to ground through a 6.04K 1% resistor."
      },
      {
        "number": "49",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed pad (VSS) on the bottom of the LAN7430 48-SQFN is not a numbered pin in Table 3-1 and is",
          "33/49 pins cited to the wrong page (name found elsewhere): ['9:AVDDL_2@p24', '12:AVDDH_2@p23', '13:VDD12CORE@p24', '14:VP@p24']",
          "1/49 pin names appear NOWHERE in the datasheet text: ['46:XO@p21']"
        ],
        "pages_sent": 38,
        "cost_usd": 0.0611,
        "at": "2026-10-27T06:48:44"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/3aae0fa39559c93683db0bdc8262e5dd.pdf",
        "pages": 77,
        "sha256": "ad01b0713999a060",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lan7430.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-10-27",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lan7430-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "13477da5d79289eaf8212dced7aaef94c515f8bbded62c17667e24f966093e31",
        "checked": "2026-10-27",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}