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LAN7430

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Microchip Tech Interface - Specialized, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232lan7430factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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LAN7430

Microchip Tech · Interface - Specialized · QFN-48-EP(7x7)

LAN7430 from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDH_1 power_in 2.5V or 3.3V power for analog IO; on the LAN7430 it powers the Gigabit PHY transmitter, bandgap reference, and crystal oscillator amplifier.
2 TXRXP_A bidirectional Media Dependent Interface[0] positive signal of the differential pair for Gigabit Ethernet channel A.
3 TXRXM_A bidirectional Media Dependent Interface[0] negative signal of the differential pair for Gigabit Ethernet channel A.
4 AVDDL_1 power_in 1.2V power for the analog core of the Ethernet PHY.
5 TXRXP_B bidirectional Media Dependent Interface[1] positive signal of the differential pair for Gigabit Ethernet channel B.
6 TXRXM_B bidirectional Media Dependent Interface[1] negative signal of the differential pair for Gigabit Ethernet channel B.
7 TXRXP_C bidirectional Media Dependent Interface[2] positive signal of the differential pair for Gigabit Ethernet channel C; not used in 10BT/100BT mode.
8 TXRXM_C bidirectional Media Dependent Interface[2] negative signal of the differential pair for Gigabit Ethernet channel C; not used in 10BT/100BT mode.
9 AVDDL_2 power_in Additional 1.2V power pin for the analog core (LAN7430 only).
10 TXRXP_D bidirectional Media Dependent Interface[3] positive signal of the differential pair for Gigabit Ethernet channel D; not used in 10BT/100BT mode.
11 TXRXM_D bidirectional Media Dependent Interface[3] negative signal of the differential pair for Gigabit Ethernet channel D; not used in 10BT/100BT mode.
12 AVDDH_2 power_in 2.5V or 3.3V power for analog IO; on the LAN7430 it provides power for the Gigabit PHY transmitter.
13 VDD12CORE power_in 1.2V digital core power supply input.
14 VP power_in 1.2V PCIe PHY analog and digital power.
15 GD_1 power_in PCIe ground.
16 PCIE_RX_P input PCIe serial data input positive, a differential input link running at 2.5 GT/s.
17 PCIE_RX_M input PCIe serial data input negative, a differential input link running at 2.5 GT/s.
18 GD_2 power_in PCIe ground.
19 PCIE_TX_P output PCIe serial data output positive, a differential output link running at 2.5 GT/s; a series capacitor of 100nF to 200nF is required.
20 VPTX power_in 1.2V PCIe PHY transmit power.
21 PCIE_TX_M output PCIe serial data output negative, a differential output link running at 2.5 GT/s; a series capacitor of 100nF to 200nF is required.
22 GD_3 power_in PCIe ground.
23 VPH power_in 2.5V PCIe PHY high voltage power.
24 RESREF input External reference resistor pin that must be connected to ground through a 200 ohm 1% 100 ppm/C resistor.
25 PCIE_CLK_P input PCIe differential reference clock input positive, which receives a 100 MHz differential clock.
26 PCIE_CLK_M input PCIe differential reference clock input negative, which receives a 100 MHz differential clock.
27 VDD25_REG_OUT power_out 2.5V output from the integrated LDO, used to power the PCIe PHY and optionally the Gigabit Ethernet PHY AFE; the LDO requires a 1.0 uF 0.1-ohm ESR capacitor on this pin.
28 VDD_REG_IN power_in 3.3V input supply to the integrated LDO; if set to 2.5V it must be externally connected to VDD25_REG_OUT.
29 RESET_N input System reset input that is active low; if unused it must be pulled up to VDDVARIO.
30 TEST input Test mode enable pin that must be connected to ground for proper functional operation.
31 VDD12CORE power_in 1.2V digital core power supply input.
32 VDD12_SW_OUT power_out 1.2V unfiltered output voltage from the integrated switching regulator, which requires an external LC filter.
33 VDD_SW_IN power_in 1.8V to 3.3V input voltage for the integrated switching regulator.
34 VDD12_SW_FB power_in Feedback pin for the integrated switching regulator; tie to VDD_SW_IN to disable the regulator.
35 VAUX_DET/GPIO3/LED3/TCK bidirectional Auxiliary voltage detect input that indicates PME from D3cold support when tied to 3.3V, and is not supported when tied to VSS; it is multiplexed with GPIO3, LED3, and TCK.
36 EECLK/GPIO2/LED2/TMS/ADV_PM_DISABLE bidirectional EEPROM clock output that drives the external EEPROM clock input; it is multiplexed with GPIO2, LED2, TMS, and the ADV_PM_DISABLE configuration strap.
37 EEDIO/GPIO1/LED1/TDO bidirectional Bidirectional EEPROM data pin that requires an external resistor on the EEPROM data output to prevent read contention; it is multiplexed with GPIO1, LED1, and TDO.
38 EECS/GPIO0/LED0/TDI bidirectional EEPROM chip select output that drives the external EEPROM chip select input; it is multiplexed with GPIO0, LED0, and TDI.
39 VDDVARIO power_in 1.8V to 3.3V variable supply for the I/Os.
40 VDD12CORE power_in 1.2V digital core power supply input.
41 VDD_OTP power_in 3.3V supply to the OTP charge pump.
42 CLKREQ# bidirectional Open-drain clock request signal used to power manage the link clock and for L1 substate control.
43 WAKE# bidirectional PCIe wake signal that is driven low when the device detects a wakeup; it is isolated from the PCIe bus when the device is powered down.
44 PERST# input PCIe reset input indicating that both PCIe power and clock are available.
45 AVDD12 power_in 1.2V power supply for the PLL and DLL.
46 XO output Crystal output that connects to one lead of a 25MHz crystal; it is not connected when an oscillator or external clock is used.
47 XI input Crystal input that connects to a 25MHz crystal or receives a 3.3V oscillator or external reference clock with ±50ppm tolerance.
48 ISET input External PHY bias resistor pin that must be connected to ground through a 6.04K 1% resistor.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDVARIO, VDDVARIO_B, VDD_SW_IN, VDD_REG_IN, VDD_OTP) -0.5 4.6 V 48
+2.5/3.3 V Analog Supply Voltage (AVDDH_1, AVDDH_2) -0.5 4.6 V 48
+2.5 V Analog Supply Voltage (VPH) -0.5 3.2 V 48
+1.2 V Analog Supply Voltage (AVDD12, AVDDL_1, AVDDL_2, VPTX, VP) -0.5 1.5 V 48
+1.2 V Digital Supply Voltage (VDD12CORE) -0.5 1.5 V 48
Positive voltage on input signal pins, with respect to ground 4.6 V 48
Negative voltage on input signal pins, with respect to ground -0.5 V 48
Storage Temperature -65 150 °C 48
HBM ESD Performance -2 2 kV 48
Supply Voltage (VDD_SW_IN) 1.62 3.63 V 48
Supply Voltage (VDDVARIO, VDDVARIO_B) 1.62 3.63 V 48
Supply Voltage (VDD_REG_IN, VDD_OTP) 2.97 3.63 V 48
+2.5/3.3 V Ethernet PHY Analog Supply Voltage (AVDDH_1, AVDDH_2) 2.33 2.75 V 48
+2.5/3.3 V Ethernet PHY Analog Supply Voltage (AVDDH_1, AVDDH_2), 3.3 V option 2.97 3.63 V 48
+2.5 V PCIe PHY Analog Supply Voltage (VPH) 2.33 2.75 V 48
+1.2 V PCIe PHY Analog Supply Voltage (VPTX, VP) 1.12 1.32 V 48
+1.2 V Ethernet PHY Analog Supply Voltage (AVDD12, AVDDL_1, AVDDL_2) 1.14 1.32 V 48
Digital Supply Voltage (VDD12CORE) 1.14 1.32 V 48
Positive voltage on input signal pins, with respect to ground (operating) 3.63 V 48
Negative voltage on input signal pins, with respect to ground (operating) -0.3 V 48
Input Low Input Level (Non-variable I/O, IS type) VIL 0.8 V Schmitt trigger 52
Input High Input Level (Non-variable I/O, IS type) VIH 2 V Schmitt trigger 52
Schmitt Trigger Hysteresis (VIHT - VILT), IS type VHYS 100 127 245 mV Schmitt trigger 52
Input Leakage (VIN = VSS or VDD_OTP), IS type IIH -10 10 µA Note 7-4 52
Input Capacitance, IS type CIN 2 3 pF Note 7-4 52
Low Output Level, OD4 type buffer VOL 0.2 V IOL = -4 mA 52
Low Input Level, ICLK type input buffer VIL 0.5 V Note 7-5 52
High Input Level, ICLK type input buffer VIH 2 V Note 7-5 52
Input Leakage, ICLK type input buffer IIH -10 10 µA Note 7-5 52
Input Leakage (VIN = VSS or VDDVARIO), VIS type IIH -10 10 µA Note 7-6 53
Low Output Level, VO8 type buffer VOL 0.4 V IOL = -8 mA 53
Low Output Level, VOD8 type buffer VOL 0.4 V IOL = -8 mA 53
Low Output Level, VO12 type buffer VOL 0.4 V IOL = -12 mA 53
Low Output Level, VOD12 type buffer VOL 0.4 V IOL = -12 mA 53
Peak Differential Output Voltage, 1000BASE-T (IEEE 802.3 clause 40.6.1.2.1) VSS 1 % Note 7-7 54
Signal Scaling, 1000BASE-T (IEEE 802.3 clause 40.6.1.2.1) VSC 2 % Note 7-8 54
Transmission Distortion, 1000BASE-T (IEEE 802.3 clause 40.6.1.2.4) 10 mV Note 7-9 54
Peak Differential Output Voltage, 100BASE-TX (ANSI X3.263 clause 9.1.2.2) VOUT -1.05 1.05 V Note 7-10 55
Signal Amplitude Symmetry, 100BASE-TX (ANSI X3.263 clause 9.1.4) VSS 2 % Note 7-10 55
Signal Rise and Fall Time, 100BASE-TX (ANSI X3.263 clause 9.1.6) TRF 3 5 nS Note 7-10 55
Rise and Fall Symmetry, 100BASE-TX (ANSI X3.263 clause 9.1.6) TRFS 0.5 nS Note 7-10 55
Duty Cycle Distortion, 100BASE-TX (ANSI X3.263 clause 9.1.8) DCD -0.25 0.25 nS Note 7-11 55
Overshoot and Undershoot, 100BASE-TX (ANSI X3.263 clause 9.1.3) VOS 5 % 55
Reference Voltage of ISET (using 6.04kΩ 1% resistor), 100BASE-TX VSET 0.65 V using 6.04kΩ 1% resistor 55
Transmitter Peak Differential Output Voltage, 10BASE-T (IEEE 802.3 clause 14.3.1.2.1) VOUT 2.2 2.5 2.8 V Note 7-13 55
Receiver Input Leakage (terminations off), PCIe III 2 µA terminations off 55
Transmitter Input Leakage, PCIe III 25 µA 55
PCIe Clock Input Leakage III 32 nA 55
Power supply turn on time tpon 50 ms 57
Power supply turn off time tpoff 500 ms 57
Configuration strap hold after external power supply at operational level tcsh 22 ms 57
Output drive after straps latched todad 3 µs 57
RESET_N input assertion time trstia 1 µs 58
Configuration strap setup before RESET_N deassertion tcss 200 ns 58
Configuration strap hold after RESET_N deassertion tcsh 10 ns 58
Output drive after RESET_N deassertion todad 3 µs 58
Frequency (fundamental, 25 MHz crystal) Ffund 25 MHz 68
Frequency Tolerance @ 25oC Ftol -50 50 PPM @ 25oC 68
Frequency Stability Over Temp Ftemp -50 50 PPM 68
Total Allowable PPM Budget -50 50 PPM 68
Shunt Capacitance CO 6 pF 68
Load Capacitance CL 25 pF 68
Drive Level PW 100 µW 68
Equivalent Series Resistance R1 50 Ohm 68
JA (thermal resistance, 48-SQFN) JA 26.4 °C/W Velocity 0 m/s 49
JA (thermal resistance, 48-SQFN) JA 23.1 °C/W Velocity 1 m/s 49
JT (thermal characterization, 48-SQFN) JT 0.2 °C/W Velocity 0 m/s 49
JT (thermal characterization, 48-SQFN) JT 0.3 °C/W Velocity 1 m/s 49
JC (thermal resistance junction-to-case, 48-SQFN) JC 1.8 °C/W N/A 49

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa • Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/ 35

CAD (KiCad official)

  • Symbol: LAN7430
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: lan7430-etched.step / lan7430-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan7430.step / lan7430.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (77 pp, sha256 ad01b0713999a060, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF