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L9663-TR-1
Public Made by Adomby adom
STMicroelectronics Interface - Specialized, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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L9663-TR-1
STMicroelectronics · Interface - Specialized · QFN-28-EP(5x5)
L9663-TR-1 from STMicroelectronics, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC1 | input | Direct interface sync pulse trigger input for transceiver 1, with a pin voltage range of -0.3 V to 6.5 V. |
| 2 | DOUT1 | output | Direct interface 1 output, also used as Interrupt 1; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 3 | CLKIN | input | External clock input; the pin voltage range is -0.3 V to 6.5 V. |
| 4 | SYNC2 | input | Direct interface sync pulse trigger input for transceiver 2, with a pin voltage range of -0.3 V to 6.5 V. |
| 5 | DOUT2 | output | Direct interface 2 output, also used as Interrupt 2; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 6 | NC(1) | unconnected | Not connected internally; must be left open. |
| 7 | BH1 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |
| 8 | BL1 | bidirectional | Bootstrap capacitor pin 2 for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |
| 9 | GND1 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND2 and the reference for all analog voltages. |
| 10 | PSI1 | bidirectional | PSI5 interface 1 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |
| 11 | VAS | power_out | PSI5 pre-regulated voltage supply, selectable as 5.3 V or 7.6 V by SPI; absolute voltage range -0.3 V to 40 V. |
| 12 | PSI2 | bidirectional | PSI5 interface 2 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |
| 13 | GND2 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND1 and the reference for all analog voltages. |
| 14 | BL2 | bidirectional | Bootstrap capacitor pin 2 for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |
| 15 | BH2 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |
| 16 | VB | power_in | Input voltage supply for the IC; absolute range -0.3 V to 40 V, with an operating voltage of 4.8 V (5.2 V for sync pulses) to 35 V. |
| 17 | VASSUP | power_in | Supply for the VAS pre-regulator and charge pump; absolute voltage range -0.3 V to 40 V. |
| 18 | VGS | bidirectional | Gate driver pin for the external n-channel FET of the VAS pre-regulator; absolute voltage range -0.3 V to 40 V. |
| 19 | NC(2) | unconnected | Not connected internally; it can be connected to GND externally. |
| 20 | MOSI | input | SPI data input; the pin voltage range is -0.3 V to 6.5 V. |
| 21 | SCLK | input | SPI clock input; the pin voltage range is -0.3 V to 6.5 V. |
| 22 | CS | input | SPI chip select input; the pin voltage range is -0.3 V to 6.5 V. |
| 23 | RESETN | input | Reset input; while RESETN is low the PSIx lines are deactivated, with a pin voltage range of -0.3 V to 6.5 V. |
| 24 | TM | input | Test-mode pin that must be connected to GND for safety reasons; the pin voltage range is -0.3 V to 6.5 V. |
| 25 | VINTD | power_out | Internal digital supply generated by the IC, requiring a 100 nF ceramic decoupling capacitor to DGND; absolute range -0.3 V to 4.6 V. |
| 26 | DGND | power_in | Ground return for the digital part; all digital voltages are related to DGND. |
| 27 | VDD | power_in | Digital I/O supply, requiring a 100 nF blocking capacitor close to the pin; absolute range -0.3 V to 6.5 V. |
| 28 | MISO | output | SPI data output; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | QFN-28-EP(5x5) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
L9663-TR-1 - Footprint:
Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm - 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
l9663-tr-1-etched.step/l9663-tr-1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l9663-tr-1.step/l9663-tr-1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (105 pp, sha256
d50c4b39968475f0, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# L9663-TR-1
**STMicroelectronics** · Interface - Specialized · QFN-28-EP(5x5)
L9663-TR-1 from STMicroelectronics, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC1 | input | Direct interface sync pulse trigger input for transceiver 1, with a pin voltage range of -0.3 V to 6.5 V. |
| 2 | DOUT1 | output | Direct interface 1 output, also used as Interrupt 1; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 3 | CLKIN | input | External clock input; the pin voltage range is -0.3 V to 6.5 V. |
| 4 | SYNC2 | input | Direct interface sync pulse trigger input for transceiver 2, with a pin voltage range of -0.3 V to 6.5 V. |
| 5 | DOUT2 | output | Direct interface 2 output, also used as Interrupt 2; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 6 | NC(1) | unconnected | Not connected internally; must be left open. |
| 7 | BH1 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |
| 8 | BL1 | bidirectional | Bootstrap capacitor pin 2 for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |
| 9 | GND1 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND2 and the reference for all analog voltages. |
| 10 | PSI1 | bidirectional | PSI5 interface 1 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |
| 11 | VAS | power_out | PSI5 pre-regulated voltage supply, selectable as 5.3 V or 7.6 V by SPI; absolute voltage range -0.3 V to 40 V. |
| 12 | PSI2 | bidirectional | PSI5 interface 2 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |
| 13 | GND2 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND1 and the reference for all analog voltages. |
| 14 | BL2 | bidirectional | Bootstrap capacitor pin 2 for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |
| 15 | BH2 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |
| 16 | VB | power_in | Input voltage supply for the IC; absolute range -0.3 V to 40 V, with an operating voltage of 4.8 V (5.2 V for sync pulses) to 35 V. |
| 17 | VASSUP | power_in | Supply for the VAS pre-regulator and charge pump; absolute voltage range -0.3 V to 40 V. |
| 18 | VGS | bidirectional | Gate driver pin for the external n-channel FET of the VAS pre-regulator; absolute voltage range -0.3 V to 40 V. |
| 19 | NC(2) | unconnected | Not connected internally; it can be connected to GND externally. |
| 20 | MOSI | input | SPI data input; the pin voltage range is -0.3 V to 6.5 V. |
| 21 | SCLK | input | SPI clock input; the pin voltage range is -0.3 V to 6.5 V. |
| 22 | CS | input | SPI chip select input; the pin voltage range is -0.3 V to 6.5 V. |
| 23 | RESETN | input | Reset input; while RESETN is low the PSIx lines are deactivated, with a pin voltage range of -0.3 V to 6.5 V. |
| 24 | TM | input | Test-mode pin that must be connected to GND for safety reasons; the pin voltage range is -0.3 V to 6.5 V. |
| 25 | VINTD | power_out | Internal digital supply generated by the IC, requiring a 100 nF ceramic decoupling capacitor to DGND; absolute range -0.3 V to 4.6 V. |
| 26 | DGND | power_in | Ground return for the digital part; all digital voltages are related to DGND. |
| 27 | VDD | power_in | Digital I/O supply, requiring a 100 nF blocking capacitor close to the pin; absolute range -0.3 V to 6.5 V. |
| 28 | MISO | output | SPI data output; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | QFN-28-EP(5x5) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 29 |
## CAD (KiCad official)
- Symbol: `L9663-TR-1`
- Footprint: `Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm`
- 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `l9663-tr-1-etched.step` / `l9663-tr-1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l9663-tr-1.step` / `l9663-tr-1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923832790339584) (105 pp, sha256 `d50c4b39968475f0`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/l9663-tr-1-datasheet.pdf)