component
L9663-TR-1
Public Made by Adomby adom
STMicroelectronics Interface - Specialized, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# L9663-TR-1++**STMicroelectronics** · Interface - Specialized · QFN-28-EP(5x5)++L9663-TR-1 from STMicroelectronics, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SYNC1 | input | Direct interface sync pulse trigger input for transceiver 1, with a pin voltage range of -0.3 V to 6.5 V. |+| 2 | DOUT1 | output | Direct interface 1 output, also used as Interrupt 1; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |+| 3 | CLKIN | input | External clock input; the pin voltage range is -0.3 V to 6.5 V. |+| 4 | SYNC2 | input | Direct interface sync pulse trigger input for transceiver 2, with a pin voltage range of -0.3 V to 6.5 V. |+| 5 | DOUT2 | output | Direct interface 2 output, also used as Interrupt 2; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |+| 6 | NC(1) | unconnected | Not connected internally; must be left open. |+| 7 | BH1 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |+| 8 | BL1 | bidirectional | Bootstrap capacitor pin 2 for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx. |+| 9 | GND1 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND2 and the reference for all analog voltages. |+| 10 | PSI1 | bidirectional | PSI5 interface 1 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |+| 11 | VAS | power_out | PSI5 pre-regulated voltage supply, selectable as 5.3 V or 7.6 V by SPI; absolute voltage range -0.3 V to 40 V. |+| 12 | PSI2 | bidirectional | PSI5 interface 2 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift. |+| 13 | GND2 | power_in | Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND1 and the reference for all analog voltages. |+| 14 | BL2 | bidirectional | Bootstrap capacitor pin 2 for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |+| 15 | BH2 | bidirectional | Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx. |+| 16 | VB | power_in | Input voltage supply for the IC; absolute range -0.3 V to 40 V, with an operating voltage of 4.8 V (5.2 V for sync pulses) to 35 V. |+| 17 | VASSUP | power_in | Supply for the VAS pre-regulator and charge pump; absolute voltage range -0.3 V to 40 V. |+| 18 | VGS | bidirectional | Gate driver pin for the external n-channel FET of the VAS pre-regulator; absolute voltage range -0.3 V to 40 V. |+| 19 | NC(2) | unconnected | Not connected internally; it can be connected to GND externally. |+| 20 | MOSI | input | SPI data input; the pin voltage range is -0.3 V to 6.5 V. |+| 21 | SCLK | input | SPI clock input; the pin voltage range is -0.3 V to 6.5 V. |+| 22 | CS | input | SPI chip select input; the pin voltage range is -0.3 V to 6.5 V. |+| 23 | RESETN | input | Reset input; while RESETN is low the PSIx lines are deactivated, with a pin voltage range of -0.3 V to 6.5 V. |+| 24 | TM | input | Test-mode pin that must be connected to GND for safety reasons; the pin voltage range is -0.3 V to 6.5 V. |+| 25 | VINTD | power_out | Internal digital supply generated by the IC, requiring a 100 nF ceramic decoupling capacitor to DGND; absolute range -0.3 V to 4.6 V. |+| 26 | DGND | power_in | Ground return for the digital part; all digital voltages are related to DGND. |+| 27 | VDD | power_in | Digital I/O supply, requiring a 100 nF blocking capacitor close to the pin; absolute range -0.3 V to 6.5 V. |+| 28 | MISO | output | SPI data output; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | QFN-28-EP(5x5) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `L9663-TR-1`+- Footprint: `Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm`+- 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `l9663-tr-1-etched.step` / `l9663-tr-1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l9663-tr-1.step` / `l9663-tr-1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923832790339584) (105 pp, sha256 `d50c4b39968475f0`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/l9663-tr-1-datasheet.pdf)
page.jsonadded+327@@ -0,0 +1,327 @@+{+ "slug": "l9663-tr-1",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Interface - Specialized, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "l9663-tr-1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "l9663-tr-1.kicad_sym",+ "l9663-tr-1.kicad_mod",+ "l9663-tr-1.glb",+ "l9663-tr-1.step",+ "l9663-tr-1.lbr",+ "docs/hero.png",+ "docs/l9663-tr-1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "l9663-tr-1-hero.glb",+ "l9663-tr-1-hero.overlay.json"+ ],+ "component": {+ "mpn": "L9663-TR-1",+ "manufacturer": "STMicroelectronics",+ "package": "QFN-28-EP(5x5)",+ "pin_count": 29,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "Interface - Specialized",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923832790339584",+ "parts": {+ "symbol": "l9663-tr-1.kicad_sym",+ "footprint": "l9663-tr-1.kicad_mod",+ "model_3d": "l9663-tr-1-hero.glb",+ "model_3d_plain": "l9663-tr-1.glb",+ "model_3d_step": "l9663-tr-1-etched.step",+ "model_3d_step_plain": "l9663-tr-1.step",+ "lbr": "l9663-tr-1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2674111",+ "digikey": "L9663-TR-1-ND",+ "mouser": "511-L9663-TR-1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:12:39Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "L9663-TR-1-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-L9663-TR-1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SYNC1",+ "type": "input",+ "description": "Direct interface sync pulse trigger input for transceiver 1, with a pin voltage range of -0.3 V to 6.5 V."+ },+ {+ "number": "2",+ "name": "DOUT1",+ "type": "output",+ "description": "Direct interface 1 output, also used as Interrupt 1; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V."+ },+ {+ "number": "3",+ "name": "CLKIN",+ "type": "input",+ "description": "External clock input; the pin voltage range is -0.3 V to 6.5 V."+ },+ {+ "number": "4",+ "name": "SYNC2",+ "type": "input",+ "description": "Direct interface sync pulse trigger input for transceiver 2, with a pin voltage range of -0.3 V to 6.5 V."+ },+ {+ "number": "5",+ "name": "DOUT2",+ "type": "output",+ "description": "Direct interface 2 output, also used as Interrupt 2; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V."+ },+ {+ "number": "6",+ "name": "NC(1)",+ "type": "unconnected",+ "description": "Not connected internally; must be left open."+ },+ {+ "number": "7",+ "name": "BH1",+ "type": "bidirectional",+ "description": "Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx."+ },+ {+ "number": "8",+ "name": "BL1",+ "type": "bidirectional",+ "description": "Bootstrap capacitor pin 2 for transceiver 1; voltage range -0.3 V to 40 V for BHx/BLx."+ },+ {+ "number": "9",+ "name": "GND1",+ "type": "power_in",+ "description": "Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND2 and the reference for all analog voltages."+ },+ {+ "number": "10",+ "name": "PSI1",+ "type": "bidirectional",+ "description": "PSI5 interface 1 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift."+ },+ {+ "number": "11",+ "name": "VAS",+ "type": "power_out",+ "description": "PSI5 pre-regulated voltage supply, selectable as 5.3 V or 7.6 V by SPI; absolute voltage range -0.3 V to 40 V."+ },+ {+ "number": "12",+ "name": "PSI2",+ "type": "bidirectional",+ "description": "PSI5 interface 2 line; voltage range -1.5 V to 40 V, and the channel is short-to-ground tolerant with ±1.5 V ground shift."+ },+ {+ "number": "13",+ "name": "GND2",+ "type": "power_in",+ "description": "Ground return for the PSI5 interface (analog and substrate ground), internally shorted to GND1 and the reference for all analog voltages."+ },+ {+ "number": "14",+ "name": "BL2",+ "type": "bidirectional",+ "description": "Bootstrap capacitor pin 2 for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx."+ },+ {+ "number": "15",+ "name": "BH2",+ "type": "bidirectional",+ "description": "Bootstrap capacitor pin 1 or SYNC voltage supply from the ECU for transceiver 2; voltage range -0.3 V to 40 V for BHx/BLx."+ },+ {+ "number": "16",+ "name": "VB",+ "type": "power_in",+ "description": "Input voltage supply for the IC; absolute range -0.3 V to 40 V, with an operating voltage of 4.8 V (5.2 V for sync pulses) to 35 V."+ },+ {+ "number": "17",+ "name": "VASSUP",+ "type": "power_in",+ "description": "Supply for the VAS pre-regulator and charge pump; absolute voltage range -0.3 V to 40 V."+ },+ {+ "number": "18",+ "name": "VGS",+ "type": "bidirectional",+ "description": "Gate driver pin for the external n-channel FET of the VAS pre-regulator; absolute voltage range -0.3 V to 40 V."+ },+ {+ "number": "19",+ "name": "NC(2)",+ "type": "unconnected",+ "description": "Not connected internally; it can be connected to GND externally."+ },+ {+ "number": "20",+ "name": "MOSI",+ "type": "input",+ "description": "SPI data input; the pin voltage range is -0.3 V to 6.5 V."+ },+ {+ "number": "21",+ "name": "SCLK",+ "type": "input",+ "description": "SPI clock input; the pin voltage range is -0.3 V to 6.5 V."+ },+ {+ "number": "22",+ "name": "CS",+ "type": "input",+ "description": "SPI chip select input; the pin voltage range is -0.3 V to 6.5 V."+ },+ {+ "number": "23",+ "name": "RESETN",+ "type": "input",+ "description": "Reset input; while RESETN is low the PSIx lines are deactivated, with a pin voltage range of -0.3 V to 6.5 V."+ },+ {+ "number": "24",+ "name": "TM",+ "type": "input",+ "description": "Test-mode pin that must be connected to GND for safety reasons; the pin voltage range is -0.3 V to 6.5 V."+ },+ {+ "number": "25",+ "name": "VINTD",+ "type": "power_out",+ "description": "Internal digital supply generated by the IC, requiring a 100 nF ceramic decoupling capacitor to DGND; absolute range -0.3 V to 4.6 V."+ },+ {+ "number": "26",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground return for the digital part; all digital voltages are related to DGND."+ },+ {+ "number": "27",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital I/O supply, requiring a 100 nF blocking capacitor close to the pin; absolute range -0.3 V to 6.5 V."+ },+ {+ "number": "28",+ "name": "MISO",+ "type": "output",+ "description": "SPI data output; the pin range is -0.3 V to VDD+0.3 V, not exceeding 6.5 V."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Order code L9663-TR-1 is listed in Table 1 as Tape & Reel for the VFQFPN28 package (L9663-1 is the V; The VFQFPN28 pin table and figure do not list or describe an exposed pad connection. The exposed-pad; Pin 11 VAS is typed power_out because the pre-regulator can generate it, but the datasheet lists it ",+ "exposed pad 29 added from the footprint"+ ],+ "pages_sent": 21,+ "cost_usd": 0.108,+ "at": "2026-10-08T02:12:21"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923832790339584",+ "pages": 105,+ "sha256": "d50c4b39968475f0",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "l9663-tr-1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e9d6d740f505b03e5aa0ac826330f9e269344b84656d051f50eb07ac162749eb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "l9663-tr-1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "1015ec873f03c8f77ed9141421edee28818d7f1d81d1826b1872c67a04ede396",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}