# L8550PLT1G

**LRC** · Bipolar (BJT) · SOT-23

L8550PLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base terminal of the PNP silicon general-purpose transistor, with emitter-base breakdown voltage of -5 V minimum at IE = -100 µA and emitter cutoff current of -150 nA maximum at VEB = -4 V. |
| 2 | EMITTER | passive | Emitter terminal of the PNP transistor, rated with a maximum emitter cutoff current of -150 nA at VEB = -4 V and emitter-base breakdown of -5 V minimum. |
| 3 | COLLECTOR | passive | Collector terminal of the PNP transistor, rated for VCEO of -25 V, VCBO of -40 V, and continuous collector current of -800 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Current Gain (P grade) | HFE | 100 |  | 200 |  | IC=-100mA, VCE=-1V | 2 |
| Collector-Emitter Saturation Voltage | VCE(S) |  |  | -0.5 | V | IC=-800mA, IB=-80mA | 2 |
| Collector-Emitter Breakdown Voltage | V(BR)CEO | -25 |  |  | V | IC=-1.0mA | 2 |
| Emitter-Base Breakdown Voltage | V(BR)EBO | -5 |  |  | V | IE=-100µA | 2 |
| Collector-Base Breakdown Voltage | V(BR)CBO | -40 |  |  | V | IC=-100µA | 2 |
| Collector Cutoff Current | ICBO |  |  | -150 | nA | VCB=-35V | 2 |
| Emitter Cutoff Current | IEBO |  |  | -150 | nA | VEB=-4V | 2 |
| Collector-Emitter Voltage | VCEO |  |  | -25 | V |  | 1 |
| Collector-Base Voltage | VCBO |  |  | -40 | V |  | 1 |
| Emitter-Base Voltage | VEBO |  |  | -5 | V |  | 1 |
| Collector Current, Continuous | IC |  |  | -800 | mAdc |  | 1 |
| Total Device Dissipation, FR-5 Board | PD |  |  | 225 | mW | TA = 25 °C | 1 |
| Derate above 25 °C, FR-5 Board |  |  |  | 1.8 | mW/°C |  | 1 |
| Thermal Resistance, Junction to Ambient, FR-5 Board | RθJA |  |  | 556 | °C/W |  | 1 |
| Total Device Dissipation, Alumina Substrate | PD |  |  | 300 | mW | TA = 25 °C | 1 |
| Derate above 25 °C, Alumina Substrate |  |  |  | 2.4 | mW/°C |  | 1 |
| Thermal Resistance, Junction to Ambient, Alumina Substrate | RθJA |  |  | 417 | °C/W |  | 1 |
| Junction and Storage Temperature | TJ, Tstg | -55 |  | 150 | °C |  | 1 |

## CAD (KiCad official)

- Symbol: `L8550PLT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `l8550plt1g-etched.step` / `l8550plt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l8550plt1g.step` / `l8550plt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182854606786560) (4 pp, sha256 `4204f6222aafe4de`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l8550plt1g-datasheet.pdf)