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L6591TR
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STMicroelectronics AC-DC Controllers And Regulators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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L6591TR
STMicroelectronics · AC-DC Controllers And Regulators · SO-16
L6591TR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LINE | input | Line sensing input tied to the high-voltage bus through a resistor divider; below 1.25 V it shuts the IC down and discharges the soft-start capacitor, with a 15 µA hysteresis current source, and it should be tied to Vcc through 220 to 330 kΩ if unused. |
| 2 | DIS | input | Latched device shutdown input that shuts the IC down and latches it when the voltage exceeds 4.5 V, with the latch cleared only when Vcc falls below the UVLO threshold; connect to GND if unused. |
| 3 | ISEN | input | Current sense input for the PWM comparator with 200 ns blanking, a 0.8 V pulse-by-pulse OCP threshold and a 1.5 V hiccup-mode OCP shutdown level, with an absolute range of -3 to 7 V. |
| 4 | SS | passive | Soft-start pin where an internal 20 µA generator charges an external capacitor to ramp the duty cycle from zero, and the same capacitor sets the delay before OCP shutdown; it is quickly discharged in UVLO. |
| 5 | OSC | passive | Oscillator timing pin where a resistor to VREF and a capacitor to GND set the switching frequency and deadtime, and the capacitor should not be lower than 220 pF. |
| 6 | VREF | power_out | Voltage reference output of 5 V ±4% (all inclusive) that can supply up to 5 mA to an external circuit, with a 0.1 µF film capacitor to GND recommended for stability. |
| 7 | COMP | input | Control input for PWM regulation driven by an optocoupler phototransistor (about 0.4 mA typ.); below 1.75 V it shuts the IC down and reduces consumption, and it restarts above 1.8 V to provide burst mode at light load. |
| 8 | PFC_STOP | output | Open-drain ON/OFF control output for the PFC controller that goes low when COMP is below 1.75 V and opens above 1.8 V, is low during IC shutdown while Vcc is above the restart threshold, and is open during UVLO; leave open if unused. |
| 9 | Vcc | power_in | Supply voltage for the signal part of the IC and the low-side gate driver, charged by the internal high-voltage generator through an external electrolytic capacitor to GND, with an IC supply absolute rating of self-limited at Icc = 20 mA. |
| 10 | LVG | output | Low-side gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the lower MOSFET, actively pulled to GND during UVLO. |
| 11 | GND | power_in | Chip ground that returns both the low-side gate-drive current and the IC bias current and must be kept separate from pulsed current return paths. |
| 12 | N.C. | unconnected | High-voltage spacer pin that is not connected internally, included to meet creepage distance safety requirements on the PCB. |
| 13 | FGND | power_in | High-side floating ground that returns the high-side gate-drive current, with a floating ground voltage of -3 to VBOOT -18 V and a slew rate limit of 50 V/ns. |
| 14 | HVG | output | High-side floating gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the upper MOSFET, with a pull-down resistor to FGND (pin 13) keeping the gate off during UVLO. |
| 15 | BOOT | power_in | High-side floating supply connected to a bootstrap capacitor referenced to FGND (pin 13) and fed by an internal synchronous bootstrap diode, with a floating supply absolute range of -1 to 618 V. |
| 16 | HVSTART | input | High-voltage startup input connected directly to the rectified mains with an absolute range of -0.3 to 700 V, where a 0.8 mA internal source charges the Vcc capacitor until the startup threshold is reached. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
L6591TR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
l6591tr-etched.step/l6591tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l6591tr.step/l6591tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (41 pp, sha256
580b374e7f3f0537, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# L6591TR
**STMicroelectronics** · AC-DC Controllers And Regulators · SO-16
L6591TR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LINE | input | Line sensing input tied to the high-voltage bus through a resistor divider; below 1.25 V it shuts the IC down and discharges the soft-start capacitor, with a 15 µA hysteresis current source, and it should be tied to Vcc through 220 to 330 kΩ if unused. |
| 2 | DIS | input | Latched device shutdown input that shuts the IC down and latches it when the voltage exceeds 4.5 V, with the latch cleared only when Vcc falls below the UVLO threshold; connect to GND if unused. |
| 3 | ISEN | input | Current sense input for the PWM comparator with 200 ns blanking, a 0.8 V pulse-by-pulse OCP threshold and a 1.5 V hiccup-mode OCP shutdown level, with an absolute range of -3 to 7 V. |
| 4 | SS | passive | Soft-start pin where an internal 20 µA generator charges an external capacitor to ramp the duty cycle from zero, and the same capacitor sets the delay before OCP shutdown; it is quickly discharged in UVLO. |
| 5 | OSC | passive | Oscillator timing pin where a resistor to VREF and a capacitor to GND set the switching frequency and deadtime, and the capacitor should not be lower than 220 pF. |
| 6 | VREF | power_out | Voltage reference output of 5 V ±4% (all inclusive) that can supply up to 5 mA to an external circuit, with a 0.1 µF film capacitor to GND recommended for stability. |
| 7 | COMP | input | Control input for PWM regulation driven by an optocoupler phototransistor (about 0.4 mA typ.); below 1.75 V it shuts the IC down and reduces consumption, and it restarts above 1.8 V to provide burst mode at light load. |
| 8 | PFC_STOP | output | Open-drain ON/OFF control output for the PFC controller that goes low when COMP is below 1.75 V and opens above 1.8 V, is low during IC shutdown while Vcc is above the restart threshold, and is open during UVLO; leave open if unused. |
| 9 | Vcc | power_in | Supply voltage for the signal part of the IC and the low-side gate driver, charged by the internal high-voltage generator through an external electrolytic capacitor to GND, with an IC supply absolute rating of self-limited at Icc = 20 mA. |
| 10 | LVG | output | Low-side gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the lower MOSFET, actively pulled to GND during UVLO. |
| 11 | GND | power_in | Chip ground that returns both the low-side gate-drive current and the IC bias current and must be kept separate from pulsed current return paths. |
| 12 | N.C. | unconnected | High-voltage spacer pin that is not connected internally, included to meet creepage distance safety requirements on the PCB. |
| 13 | FGND | power_in | High-side floating ground that returns the high-side gate-drive current, with a floating ground voltage of -3 to VBOOT -18 V and a slew rate limit of 50 V/ns. |
| 14 | HVG | output | High-side floating gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the upper MOSFET, with a pull-down resistor to FGND (pin 13) keeping the gate off during UVLO. |
| 15 | BOOT | power_in | High-side floating supply connected to a bootstrap capacitor referenced to FGND (pin 13) and fed by an internal synchronous bootstrap diode, with a floating supply absolute range of -1 to 618 V. |
| 16 | HVSTART | input | High-voltage startup input connected directly to the rectified mains with an absolute range of -0.3 to 700 V, where a 0.8 mA internal source charges the Vcc capacitor until the startup threshold is reached. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `L6591TR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `l6591tr-etched.step` / `l6591tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6591tr.step` / `l6591tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603317618724532224) (41 pp, sha256 `580b374e7f3f0537`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/l6591tr-datasheet.pdf)