component
L6591TR
Public Made by Adomby adom
STMicroelectronics AC-DC Controllers And Regulators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# L6591TR++**STMicroelectronics** · AC-DC Controllers And Regulators · SO-16++L6591TR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LINE | input | Line sensing input tied to the high-voltage bus through a resistor divider; below 1.25 V it shuts the IC down and discharges the soft-start capacitor, with a 15 µA hysteresis current source, and it should be tied to Vcc through 220 to 330 kΩ if unused. |+| 2 | DIS | input | Latched device shutdown input that shuts the IC down and latches it when the voltage exceeds 4.5 V, with the latch cleared only when Vcc falls below the UVLO threshold; connect to GND if unused. |+| 3 | ISEN | input | Current sense input for the PWM comparator with 200 ns blanking, a 0.8 V pulse-by-pulse OCP threshold and a 1.5 V hiccup-mode OCP shutdown level, with an absolute range of -3 to 7 V. |+| 4 | SS | passive | Soft-start pin where an internal 20 µA generator charges an external capacitor to ramp the duty cycle from zero, and the same capacitor sets the delay before OCP shutdown; it is quickly discharged in UVLO. |+| 5 | OSC | passive | Oscillator timing pin where a resistor to VREF and a capacitor to GND set the switching frequency and deadtime, and the capacitor should not be lower than 220 pF. |+| 6 | VREF | power_out | Voltage reference output of 5 V ±4% (all inclusive) that can supply up to 5 mA to an external circuit, with a 0.1 µF film capacitor to GND recommended for stability. |+| 7 | COMP | input | Control input for PWM regulation driven by an optocoupler phototransistor (about 0.4 mA typ.); below 1.75 V it shuts the IC down and reduces consumption, and it restarts above 1.8 V to provide burst mode at light load. |+| 8 | PFC_STOP | output | Open-drain ON/OFF control output for the PFC controller that goes low when COMP is below 1.75 V and opens above 1.8 V, is low during IC shutdown while Vcc is above the restart threshold, and is open during UVLO; leave open if unused. |+| 9 | Vcc | power_in | Supply voltage for the signal part of the IC and the low-side gate driver, charged by the internal high-voltage generator through an external electrolytic capacitor to GND, with an IC supply absolute rating of self-limited at Icc = 20 mA. |+| 10 | LVG | output | Low-side gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the lower MOSFET, actively pulled to GND during UVLO. |+| 11 | GND | power_in | Chip ground that returns both the low-side gate-drive current and the IC bias current and must be kept separate from pulsed current return paths. |+| 12 | N.C. | unconnected | High-voltage spacer pin that is not connected internally, included to meet creepage distance safety requirements on the PCB. |+| 13 | FGND | power_in | High-side floating ground that returns the high-side gate-drive current, with a floating ground voltage of -3 to VBOOT -18 V and a slew rate limit of 50 V/ns. |+| 14 | HVG | output | High-side floating gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the upper MOSFET, with a pull-down resistor to FGND (pin 13) keeping the gate off during UVLO. |+| 15 | BOOT | power_in | High-side floating supply connected to a bootstrap capacitor referenced to FGND (pin 13) and fed by an internal synchronous bootstrap diode, with a floating supply absolute range of -1 to 618 V. |+| 16 | HVSTART | input | High-voltage startup input connected directly to the rectified mains with an absolute range of -0.3 to 700 V, where a 0.8 mA internal source charges the Vcc capacitor until the startup threshold is reached. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-16 |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `L6591TR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SO-16 (KiCad packages3D, STEP)+- 3D model files: `l6591tr-etched.step` / `l6591tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6591tr.step` / `l6591tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603317618724532224) (41 pp, sha256 `580b374e7f3f0537`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/l6591tr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "l6591tr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics AC-DC Controllers And Regulators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "l6591tr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "l6591tr.kicad_sym",+ "l6591tr.kicad_mod",+ "l6591tr.glb",+ "l6591tr.step",+ "l6591tr.lbr",+ "docs/hero.png",+ "docs/l6591tr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "l6591tr-hero.glb",+ "l6591tr-hero.overlay.json"+ ],+ "component": {+ "mpn": "L6591TR",+ "manufacturer": "STMicroelectronics",+ "package": "SO-16",+ "pin_count": 16,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603317618724532224",+ "parts": {+ "symbol": "l6591tr.kicad_sym",+ "footprint": "l6591tr.kicad_mod",+ "model_3d": "l6591tr-hero.glb",+ "model_3d_plain": "l6591tr.glb",+ "model_3d_step": "l6591tr-etched.step",+ "model_3d_step_plain": "l6591tr.step",+ "lbr": "l6591tr.lbr"+ },+ "distributor_links": {+ "lcsc": "C3093788",+ "digikey": "497-19601-2-ND",+ "mouser": "511-L6591TR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:34:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-19601-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-L6591TR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LINE",+ "type": "input",+ "description": "Line sensing input tied to the high-voltage bus through a resistor divider; below 1.25 V it shuts the IC down and discharges the soft-start capacitor, with a 15 µA hysteresis current source, and it should be tied to Vcc through 220 to 330 kΩ if unused."+ },+ {+ "number": "2",+ "name": "DIS",+ "type": "input",+ "description": "Latched device shutdown input that shuts the IC down and latches it when the voltage exceeds 4.5 V, with the latch cleared only when Vcc falls below the UVLO threshold; connect to GND if unused."+ },+ {+ "number": "3",+ "name": "ISEN",+ "type": "input",+ "description": "Current sense input for the PWM comparator with 200 ns blanking, a 0.8 V pulse-by-pulse OCP threshold and a 1.5 V hiccup-mode OCP shutdown level, with an absolute range of -3 to 7 V."+ },+ {+ "number": "4",+ "name": "SS",+ "type": "passive",+ "description": "Soft-start pin where an internal 20 µA generator charges an external capacitor to ramp the duty cycle from zero, and the same capacitor sets the delay before OCP shutdown; it is quickly discharged in UVLO."+ },+ {+ "number": "5",+ "name": "OSC",+ "type": "passive",+ "description": "Oscillator timing pin where a resistor to VREF and a capacitor to GND set the switching frequency and deadtime, and the capacitor should not be lower than 220 pF."+ },+ {+ "number": "6",+ "name": "VREF",+ "type": "power_out",+ "description": "Voltage reference output of 5 V ±4% (all inclusive) that can supply up to 5 mA to an external circuit, with a 0.1 µF film capacitor to GND recommended for stability."+ },+ {+ "number": "7",+ "name": "COMP",+ "type": "input",+ "description": "Control input for PWM regulation driven by an optocoupler phototransistor (about 0.4 mA typ.); below 1.75 V it shuts the IC down and reduces consumption, and it restarts above 1.8 V to provide burst mode at light load."+ },+ {+ "number": "8",+ "name": "PFC_STOP",+ "type": "output",+ "description": "Open-drain ON/OFF control output for the PFC controller that goes low when COMP is below 1.75 V and opens above 1.8 V, is low during IC shutdown while Vcc is above the restart threshold, and is open during UVLO; leave open if unused."+ },+ {+ "number": "9",+ "name": "Vcc",+ "type": "power_in",+ "description": "Supply voltage for the signal part of the IC and the low-side gate driver, charged by the internal high-voltage generator through an external electrolytic capacitor to GND, with an IC supply absolute rating of self-limited at Icc = 20 mA."+ },+ {+ "number": "10",+ "name": "LVG",+ "type": "output",+ "description": "Low-side gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the lower MOSFET, actively pulled to GND during UVLO."+ },+ {+ "number": "11",+ "name": "GND",+ "type": "power_in",+ "description": "Chip ground that returns both the low-side gate-drive current and the IC bias current and must be kept separate from pulsed current return paths."+ },+ {+ "number": "12",+ "name": "N.C.",+ "type": "unconnected",+ "description": "High-voltage spacer pin that is not connected internally, included to meet creepage distance safety requirements on the PCB."+ },+ {+ "number": "13",+ "name": "FGND",+ "type": "power_in",+ "description": "High-side floating ground that returns the high-side gate-drive current, with a floating ground voltage of -3 to VBOOT -18 V and a slew rate limit of 50 V/ns."+ },+ {+ "number": "14",+ "name": "HVG",+ "type": "output",+ "description": "High-side floating gate-drive output capable of 0.3 A min. source and 0.8 A min. sink peak current for the upper MOSFET, with a pull-down resistor to FGND (pin 13) keeping the gate off during UVLO."+ },+ {+ "number": "15",+ "name": "BOOT",+ "type": "power_in",+ "description": "High-side floating supply connected to a bootstrap capacitor referenced to FGND (pin 13) and fed by an internal synchronous bootstrap diode, with a floating supply absolute range of -1 to 618 V."+ },+ {+ "number": "16",+ "name": "HVSTART",+ "type": "input",+ "description": "High-voltage startup input connected directly to the rectified mains with an absolute range of -0.3 to 700 V, where a 0.8 mA internal source charges the Vcc capacitor until the startup threshold is reached."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet text provided covers only 6 of 41 pages and does not include the ordering information,; The pin connection figure (top view) lists names and numbers in a scrambled order, so the pin-to-num; The FGND floating ground voltage limit is printed as '-3 to VBOOT -18 V' in Table 2, which is ambigu"+ ],+ "pages_sent": 6,+ "cost_usd": 0.0523,+ "at": "2026-10-07T21:34:08"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603317618724532224",+ "pages": 41,+ "sha256": "580b374e7f3f0537",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "l6591tr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "l6591tr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "df83f5e8ce13b78a1f33aeb8dfa50c5934996217641562ad4b8ce004e9d9b171",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}