L4984DTR

STMicroelectronics · AC-DC Controllers And Regulators · SSOP-10-150mil

L4984DTR from STMicroelectronics, in a SSOP-10-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV	input	Inverting input of error amplifier with 2.5 V reference voltage for PFC output voltage feedback control.
2	COMP	output	Error amplifier output for voltage loop compensation with internal clamp at 2.4 V to enable burst-mode operation.
3	MULT	input	Sinusoidal reference input to multiplier for line-current shaping, operating range 0-3 V with internal clamp at 9.5 V.
4	CS	input	PWM comparator input for MOSFET drain current sensing with 220 ns digital leading-edge blanking and 1.7 V saturation detection for boost inductor protection.
5	VFF	input	Voltage feedforward input for 1/V2 line-voltage compensation with external RC network (RFF 100 kΩ-2 MΩ, CFF capacitor) and brownout detection below 0.8 V.
6	PFC_OK	input	Output voltage overvoltage protection monitor with threshold at 2.5 V, feedback failure detection when VPFC_OK > 2.5 V and VINV < 1.66 V, and disable function at 0.23 V.
7	TIMER	output	Timing capacitor node charged by 142-163 µA internal current source during MOSFET off-time to generate frequency-set ramp.
8	GND	power_in	Ground return for signal circuits and gate driver with separate PCB trace routing from sense resistor to prevent coupling with bias network grounds.
9	GD	tri_state	Totem pole gate driver output capable of 600 mA source current and 800 mA sink current with high-level output voltage clamped at 12 V.
10	VCC	power_in	Positive supply voltage (operating range 10.3-22.5 V) for signal and gate driver circuits with internal 22.5 V minimum zener clamp.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SSOP-10-150mil
Category	Power Management (PMIC)
Pins	10

CAD (KiCad official)

Symbol: L4984DTR
Footprint: Package_SO:SSOP-10_3.9x4.9mm_P1.00mm
3D model: SSOP-10-150mil (KiCad packages3D, STEP)
3D model files: l4984dtr-etched.step / l4984dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l4984dtr.step / l4984dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (35 pp, sha256 ddbe33bb11823bd2, retrieved 2026-09-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# L4984DTR

**STMicroelectronics** · AC-DC Controllers And Regulators · SSOP-10-150mil

L4984DTR from STMicroelectronics, in a SSOP-10-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV | input | Inverting input of error amplifier with 2.5 V reference voltage for PFC output voltage feedback control. |
| 2 | COMP | output | Error amplifier output for voltage loop compensation with internal clamp at 2.4 V to enable burst-mode operation. |
| 3 | MULT | input | Sinusoidal reference input to multiplier for line-current shaping, operating range 0-3 V with internal clamp at 9.5 V. |
| 4 | CS | input | PWM comparator input for MOSFET drain current sensing with 220 ns digital leading-edge blanking and 1.7 V saturation detection for boost inductor protection. |
| 5 | VFF | input | Voltage feedforward input for 1/V2 line-voltage compensation with external RC network (RFF 100 kΩ-2 MΩ, CFF capacitor) and brownout detection below 0.8 V. |
| 6 | PFC_OK | input | Output voltage overvoltage protection monitor with threshold at 2.5 V, feedback failure detection when VPFC_OK > 2.5 V and VINV < 1.66 V, and disable function at 0.23 V. |
| 7 | TIMER | output | Timing capacitor node charged by 142-163 µA internal current source during MOSFET off-time to generate frequency-set ramp. |
| 8 | GND | power_in | Ground return for signal circuits and gate driver with separate PCB trace routing from sense resistor to prevent coupling with bias network grounds. |
| 9 | GD | tri_state | Totem pole gate driver output capable of 600 mA source current and 800 mA sink current with high-level output voltage clamped at 12 V. |
| 10 | VCC | power_in | Positive supply voltage (operating range 10.3-22.5 V) for signal and gate driver circuits with internal 22.5 V minimum zener clamp. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SSOP-10-150mil |
| Category | Power Management (PMIC) |
| Pins | 10 |

## CAD (KiCad official)

- Symbol: `L4984DTR`
- Footprint: `Package_SO:SSOP-10_3.9x4.9mm_P1.00mm`
- 3D model: SSOP-10-150mil (KiCad packages3D, STEP)
- 3D model files: `l4984dtr-etched.step` / `l4984dtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l4984dtr.step` / `l4984dtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881791050788864) (35 pp, sha256 `ddbe33bb11823bd2`, retrieved 2026-09-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l4984dtr-datasheet.pdf)