# L2N7002KWT1G

**LRC** · MOSFETs · SC-70

L2N7002KWT1G from LRC, in a SC-70. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate terminal of the N-channel MOSFET, ESD protected to 2000 V HBM with a gate-source voltage limit of ±20 V. |
| 2 | Source | passive | Source terminal of the N-channel MOSFET, with a body-diode source current limit of 300 mA. |
| 3 | Drain | passive | Drain terminal of the N-channel MOSFET, rated for 60 V drain-source voltage and 320 mA steady-state drain current at 25°C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SC-70 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VBRDSS | 60 |  |  | Vdc | VGS = 0, ID = 250 μAdc | 2 |
| Gate Threshold Voltage | VGS(th) | 1 |  |  | Vdc | VDS = VGS, ID = 250 μAdc | 2 |
| Forward Transconductance | gfs | 80 |  |  | mS | VDS = 5.0 Vdc, ID = 200 mAdc | 2 |
| Gate-Source Voltage | VGS | -20 |  | 20 | Vdc |  | 1 |
| Gate-Source ESD Rating (HBM, Method 3015) |  |  |  | 2000 | V | HBM, ESD Method 3015 | 1 |
| Operating Junction and Storage Temperature | TJ,Tstg | -55 |  | 150 | ºC |  | 1 |
| Drain-Source Voltage | VDSS |  |  | 60 | Vdc |  | 1 |
| Drain Current, Steady State | ID |  |  | 320 | mAdc | Steady state, TA = 25°C | 1 |
| Drain Current, Steady State | ID |  |  | 230 | mAdc | Steady state, TA = 85°C | 1 |
| Drain Current, t<5s | ID |  |  | 380 | mAdc | t < 5 s, TA = 25°C | 1 |
| Drain Current, t<5s | ID |  |  | 270 | mAdc | t < 5 s, TA = 85°C | 1 |
| Pulsed Drain Current | IDM |  |  | 1.5 | A | tp = 10 μs | 1 |
| Source Current (Body Diode) | IS |  |  | 300 | mA |  | 1 |
| Total Device Dissipation, Steady State | PD |  |  | 300 | mW | Steady state (FR-5 board, Note 1) | 1 |
| Total Device Dissipation, t<5s | PD |  |  | 420 | mW | t < 5 s (FR-5 board, Note 1) | 1 |
| Junction-to-Ambient Thermal Resistance, Steady State | RΘJA |  |  | 417 | ºC/W | Steady state (Note 1) | 1 |
| Junction-to-Ambient Thermal Resistance, t<5s | RΘJA |  |  | 300 | ºC/W | t < 5 s (Note 1) | 1 |
| Lead Temperature for Soldering Purposes | TL |  |  | 260 | ºC | 1/8 in. from case for 10 s | 1 |

## CAD (KiCad official)

- Symbol: `L2N7002KWT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-323_SC-70`
- 3D model: SC-70 (KiCad packages3D, STEP)
- 3D model files: `l2n7002kwt1g-etched.step` / `l2n7002kwt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l2n7002kwt1g.step` / `l2n7002kwt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588954652057980928) (6 pp, sha256 `999c66e559f8cee6`, retrieved 2026-11-06, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l2n7002kwt1g-datasheet.pdf)