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KSZ9897RTXI

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Microchip Tech Interface - Specialized, TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ9897RTXI

Microchip Tech · Interface - Specialized · TQFP-128(14x14)

KSZ9897RTXI from Microchip Tech, in a TQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXRX1P_A passive Port 1 1000BASE-T differential data pair A (+); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
2 TXRX1M_A passive Port 1 1000BASE-T differential data pair A (-); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
3 AVDDL power_in +1.2V analog power supply for the PHY core.
4 TXRX1P_B passive Port 1 1000BASE-T differential data pair B (+).
5 TXRX1M_B passive Port 1 1000BASE-T differential data pair B (-).
6 TXRX1P_C passive Port 1 1000BASE-T differential data pair C (+).
7 TXRX1M_C passive Port 1 1000BASE-T differential data pair C (-).
8 TXRX1P_D passive Port 1 1000BASE-T differential data pair D (+).
9 TXRX1M_D passive Port 1 1000BASE-T differential data pair D (-).
10 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
11 DVDDL power_in +1.2V digital core power supply.
12 TXRX2P_A passive Port 2 1000BASE-T differential data pair A (+); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
13 TXRX2M_A passive Port 2 1000BASE-T differential data pair A (-); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
14 AVDDL power_in +1.2V analog power supply for the PHY core.
15 TXRX2P_B passive Port 2 1000BASE-T differential data pair B (+).
16 TXRX2M_B passive Port 2 1000BASE-T differential data pair B (-).
17 TXRX2P_C passive Port 2 1000BASE-T differential data pair C (+).
18 TXRX2M_C passive Port 2 1000BASE-T differential data pair C (-).
19 AVDDL power_in +1.2V analog power supply for the PHY core.
20 TXRX2P_D passive Port 2 1000BASE-T differential data pair D (+).
21 TXRX2M_D passive Port 2 1000BASE-T differential data pair D (-).
22 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
23 DVDDL power_in +1.2V digital core power supply.
24 TXRX3P_A passive Port 3 1000BASE-T differential data pair A (+); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
25 TXRX3M_A passive Port 3 1000BASE-T differential data pair A (-); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
26 TXRX3P_B passive Port 3 1000BASE-T differential data pair B (+).
27 TXRX3M_B passive Port 3 1000BASE-T differential data pair B (-).
28 TXRX3P_C passive Port 3 1000BASE-T differential data pair C (+).
29 TXRX3M_C passive Port 3 1000BASE-T differential data pair C (-).
30 AVDDL power_in +1.2V analog power supply for the PHY core.
31 TXRX3P_D passive Port 3 1000BASE-T differential data pair D (+).
32 TXRX3M_D passive Port 3 1000BASE-T differential data pair D (-).
33 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
34 TXRX4P_A passive Port 4 1000BASE-T differential data pair A (+); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
35 TXRX4M_A passive Port 4 1000BASE-T differential data pair A (-); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
36 AVDDL power_in +1.2V analog power supply for the PHY core.
37 TXRX4P_B passive Port 4 1000BASE-T differential data pair B (+).
38 TXRX4M_B passive Port 4 1000BASE-T differential data pair B (-).
39 TXRX4P_C passive Port 4 1000BASE-T differential data pair C (+).
40 TXRX4M_C passive Port 4 1000BASE-T differential data pair C (-).
41 AVDDL power_in +1.2V analog power supply for the PHY core.
42 TXRX4P_D passive Port 4 1000BASE-T differential data pair D (+).
43 TXRX4M_D passive Port 4 1000BASE-T differential data pair D (-).
44 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
45 DVDDL power_in +1.2V digital core power supply.
46 GND power_in Ground.
47 GND power_in Ground.
48 TX_CLK6/REFCLKI6 bidirectional Port 6 MII transmit clock (25/2.5MHz, output in PHY mode, input in MAC mode), RMII 50MHz reference clock input in Normal mode, or RGMII 125/25/2.5MHz transmit clock input.
49 TX_EN6/TX_CTL6 input Port 6 MII/RMII Transmit Enable input, or RGMII Transmit Control input.
50 TX_ER6 input Port 6 MII transmit error input; not used in RMII or RGMII modes and must not be connected in those modes.
51 COL6 bidirectional Port 6 MII collision detect (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and must not be connected in those modes.
52 TXD6_3 input Port 6 MII/RGMII transmit data bit 3; not used in RMII mode and must not be connected in that mode.
53 TXD6_2 input Port 6 MII/RGMII transmit data bit 2; not used in RMII mode and must not be connected in that mode.
54 TXD6_1 input Port 6 MII/RMII/RGMII transmit data bit 1.
55 TXD6_0 input Port 6 MII/RMII/RGMII transmit data bit 0.
56 DVDDL power_in +1.2V digital core power supply.
57 RX_CLK6/REFCLKO6 bidirectional Port 6 MII receive clock (25/2.5MHz, output in PHY mode, input in MAC mode), RMII 50MHz reference clock output in Clock mode, or RGMII 125/25/2.5MHz receive clock output.
58 RX_DV6/CRS_DV6/RX_CTL6 bidirectional Port 6 MII Receive Data Valid output, RMII Carrier Sense/Receive Data Valid output, or RGMII Receive Control output.
59 RX_ER6 bidirectional Port 6 MII receive error output; not used in RMII or RGMII modes and must not be connected in those modes.
60 CRS6 bidirectional Port 6 MII carrier sense (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and must not be connected in those modes.
61 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/O pins.
62 RXD6_3 bidirectional Port 6 MII/RGMII receive data bit 3; configuration strap pin (Port 6 mode with RXD6_2) sampled at reset.
63 RXD6_2 bidirectional Port 6 MII/RGMII receive data bit 2; configuration strap pin (Port 6 mode with RXD6_3) sampled at reset.
64 RXD6_1 bidirectional Port 6 MII/RMII/RGMII receive data bit 1; configuration strap pin (Port 6 MII/RMII PHY or MAC mode) sampled at reset.
65 RXD6_0 bidirectional Port 6 MII/RMII/RGMII receive data bit 0; configuration strap pin (Port 6 speed select) sampled at reset.
66 TX_CLK7/REFCLKI7 bidirectional Port 7 MII transmit clock (25/2.5MHz, output in PHY mode, input in MAC mode), RMII 50MHz reference clock input in Normal mode, or RGMII 125/25/2.5MHz transmit clock input.
67 TX_EN7/TX_CTL7 input Port 7 MII/RMII Transmit Enable input, or RGMII Transmit Control input.
68 TX_ER7 input Port 7 MII transmit error input; not used in RMII or RGMII modes and must not be connected in those modes.
69 COL7 bidirectional Port 7 MII collision detect (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and must not be connected in those modes.
70 TXD7_3 input Port 7 MII/RGMII transmit data bit 3; not used in RMII mode and must not be connected in that mode.
71 TXD7_2 input Port 7 MII/RGMII transmit data bit 2; not used in RMII mode and must not be connected in that mode.
72 TXD7_1 input Port 7 MII/RMII/RGMII transmit data bit 1.
73 TXD7_0 input Port 7 MII/RMII/RGMII transmit data bit 0.
74 DVDDL power_in +1.2V digital core power supply.
75 RX_CLK7/REFCLKO7 bidirectional Port 7 MII receive clock (25/2.5MHz, output in PHY mode, input in MAC mode), RMII 50MHz reference clock output in Clock mode, or RGMII 125/25/2.5MHz receive clock output.
76 RX_DV7/CRS_DV7/RX_CTL7 bidirectional Port 7 MII Receive Data Valid output, RMII Carrier Sense/Receive Data Valid output, or RGMII Receive Control output; configuration strap pin that enables In-Band Management when high at reset.
77 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/O pins.
78 RX_ER7 bidirectional Port 7 MII receive error output; not used in RMII or RGMII modes and must not be connected in those modes.
79 CRS7 bidirectional Port 7 MII carrier sense (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and must not be connected in those modes.
80 RXD7_3 bidirectional Port 7 MII/RGMII receive data bit 3; configuration strap pin (Port 7 mode with RXD7_2) sampled at reset.
81 RXD7_2 bidirectional Port 7 MII/RGMII receive data bit 2; configuration strap pin (Port 7 mode with RXD7_3) sampled at reset.
82 RXD7_1 bidirectional Port 7 MII/RMII/RGMII receive data bit 1; configuration strap pin (Port 7 MII/RMII PHY or MAC mode) sampled at reset.
83 RXD7_0 bidirectional Port 7 MII/RMII/RGMII receive data bit 0; configuration strap pin (Port 7 speed select) sampled at reset.
84 GND power_in Ground.
85 LED4_0 bidirectional Port 4 LED indicator 0, active low sink output for an external LED; configuration strap pin sampled at reset.
86 LED4_1 bidirectional Port 4 LED indicator 1, active low sink output for an external LED; configuration strap pin sampled at reset.
87 DVDDL power_in +1.2V digital core power supply.
88 LED3_0 bidirectional Port 3 LED indicator 0, active low sink output for an external LED.
89 LED3_1 bidirectional Port 3 LED indicator 1, active low sink output for an external LED; configuration strap pin sampled at reset.
90 NC unconnected No connect; must be left unconnected for proper operation.
91 LED2_0 bidirectional Port 2 LED indicator 0, active low sink output for an external LED; configuration strap pin sampled at reset.
92 LED2_1 bidirectional Port 2 LED indicator 1, active low sink output for an external LED; configuration strap pin sampled at reset.
93 PME_N output Power management event output that signals an energy detect event to wake the system; polarity is programmable (default active low) and requires an external pull-up for active-low operation.
94 INTRP_N output Active low, open-drain interrupt output that requires an external pull-up resistor.
95 CLKO_25_125 output 25/125MHz reference clock output derived from the crystal input, powered from VDDIO and可 disabled when not needed.
96 RESET_N input Active low system reset that must be asserted during or after power-on; an RC circuit is suggested for power-on reset.
97 SDO output SPI data out (MISO); not used in I2C or MIIM modes.
98 SDI/SDA/MDIO bidirectional SPI data in (SDI), I2C data (SDA) or MIIM data (MDIO); open-drain when outputting and requires an external 1.0kΩ to 4.7kΩ pull-up to VDDIO.
99 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/O pins.
100 SCS_N input SPI chip select, active low; not used in I2C or MIIM modes.
101 SCL/MDC input SPI/I2C serial clock (SCL) or MIIM serial clock (MDC) input from the host.
102 LED5_0 bidirectional Port 5 LED indicator 0, active low sink output for an external LED.
103 LED5_1 bidirectional Port 5 LED indicator 1, active low sink output for an external LED; configuration strap pin sampled at reset.
104 DVDDL power_in +1.2V digital core power supply.
105 LED1_0 bidirectional Port 1 LED indicator 0, active low sink output for an external LED.
106 LED1_1 bidirectional Port 1 LED indicator 1, active low sink output for an external LED; configuration strap pin sampled at reset.
107 GND power_in Ground.
108 NC unconnected No connect; must be left unconnected for proper operation.
109 GND power_in Ground.
110 DVDDL power_in +1.2V digital core power supply.
111 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
112 TXRX5P_A passive Port 5 1000BASE-T differential data pair A (+); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
113 TXRX5M_A passive Port 5 1000BASE-T differential data pair A (-); 100BASE-TX and 10BASE-Te are also supported on pairs A and B.
114 AVDDL power_in +1.2V analog power supply for the PHY core.
115 TXRX5P_B passive Port 5 1000BASE-T differential data pair B (+).
116 TXRX5M_B passive Port 5 1000BASE-T differential data pair B (-).
117 TXRX5P_C passive Port 5 1000BASE-T differential data pair C (+).
118 TXRX5M_C passive Port 5 1000BASE-T differential data pair C (-).
119 AVDDL power_in +1.2V analog power supply for the PHY core.
120 TXRX5P_D passive Port 5 1000BASE-T differential data pair D (+).
121 TXRX5M_D passive Port 5 1000BASE-T differential data pair D (-).
122 AVDDH power_in +2.5V analog power supply for the PHY transceivers.
123 GND power_in Ground.
124 AVDDL power_in +1.2V analog power supply for the PHY core.
125 XO output Crystal clock output connected to one lead of a 25MHz crystal; left unconnected when an external oscillator drives XI.
126 XI input 25MHz crystal or oscillator clock input with a required tolerance of ±50ppm.
127 ISET passive Transmit output current set resistor; must be connected to GND through a 6.04kΩ 1% resistor.
128 AVDDH power_in +2.5V analog power supply for the PHY transceivers.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-128(14x14)
Category Interface
Pins 128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (AVDDL, DVDDL) -0.5 1.8 V 168
Supply Voltage (AVDDH, VDDIO) -0.5 5 V 168
Input Voltage (all inputs) -0.5 5 V 168
Output Voltage (all outputs) -0.5 5 V 168
Lead Temperature (soldering) 260 °C soldering, 20 sec 168
Storage Temperature TS -65 150 °C 168
Maximum Junction Temperature TJ 125 °C 168
HBM ESD Performance -6 6 kV HBM 168
Supply Voltage (AVDDL, DVDDL) 1.14 1.26 V 168
Supply Voltage (AVDDH) 2.375 2.625 V 168
Supply Voltage (VDDIO @ 3.3V) 3.135 3.465 V 168
Supply Voltage (VDDIO @ 2.5V) 2.375 2.625 V 168
Supply Voltage (VDDIO @ 1.8V) 1.71 1.89 V 168
Ambient Operating Temperature in Still Air TA -40 85 °C Note 6-1: -40°C to +85°C for industrial version (0°C to +70°C commercial) 168
Junction to Ambient Resistance (6-layer PCB) JA 11.3 °C/W 6-layer PCB per JESD51 (Note 6-3); 0 m/s air velocity (Note 6-2) 168
Junction to Ambient Resistance (4-layer PCB) JA 14.4 °C/W 4-layer PCB per JESD51 (Note 6-3); 0 m/s air velocity (Note 6-2) 168
Junction to Case Characterization JT 0.04 °C/W 0 m/s air velocity (Note 6-2) 168
Junction to Case Resistance (6-layer PCB) JC 1.5 °C/W 6-layer PCB per JESD51 (Note 6-4) 168
Junction to Case Resistance (4-layer PCB) JC 1.21 °C/W 4-layer PCB per JESD51 (Note 6-4) 168
Input High Voltage (CMOS I buffer) VIH 2.1 V TA = 25°C; VDDIO = 3.3V 170
Input High Voltage (CMOS I buffer) VIH 1.7 V TA = 25°C; VDDIO = 2.5V 170
Input High Voltage (CMOS I buffer) VIH 1.3 V TA = 25°C; VDDIO = 1.8V 170
Input Low Voltage (CMOS I buffer) VIL 0.9 V TA = 25°C; VDDIO = 3.3V 170
Input Low Voltage (CMOS I buffer) VIL 0.6 V TA = 25°C; VDDIO = 1.8V 170
Input Current IIN -10 10 µA TA = 25°C; VIN = GND ~ VDDIO 170
Output High Voltage (O8) VOH 2.4 V TA = 25°C; IOH = 8 mA; VDDIO = 3.3V 170
Output High Voltage (O8) VOH 1.9 V TA = 25°C; IOH = 8 mA; VDDIO = 2.5V 170
Output High Voltage (O8) VOH 1.5 V TA = 25°C; IOH = 6 mA; VDDIO = 1.8V 170
Output Low Voltage (O8) VOL 0.4 V TA = 25°C; IOL = 8 mA; VDDIO = 3.3V 170
Output Low Voltage (O8) VOL 0.2 V TA = 25°C; IOL = 6 mA; VDDIO = 1.8V 170
Output Tri-State Leakage (O8) IOZ 10 µA TA = 25°C; VIN = GND ~ VDDIO 170
Output High Voltage (O24) VOH 2.4 V TA = 25°C; IOH = 24 mA; VDDIO = 3.3V 170
Output High Voltage (O24) VOH 1.9 V TA = 25°C; IOH = 24 mA; VDDIO = 2.5V 170
Output High Voltage (O24) VOH 1.5 V TA = 25°C; IOH = 20 mA; VDDIO = 1.8V 170
Output Low Voltage (O24) VOL 0.4 V TA = 25°C; IOL = 24 mA; VDDIO = 3.3V 170
Output Low Voltage (O24) VOL 0.2 V TA = 25°C; IOL = 20 mA; VDDIO = 1.8V 170
Output Tri-State Leakage (O24) IOZ 10 µA TA = 25°C; VIN = GND ~ VDDIO 170
Internal pull-up/pull-down resistance tolerance (IPU/IPD/OPU/OPD) -30 30 % Buffer types printed as 58 kΩ ±30% 6
Peak Differential Output (100BASE-TX) VO 0.95 1.05 V TA = 25°C; 100Ω termination on the differential output 170
Output Voltage Imbalance (100BASE-TX) Vimb 2 % TA = 25°C; 100Ω termination on the differential output 170
Rise/Fall Time (100BASE-TX) tr, tf 3 5 ns TA = 25°C 170
Rise/Fall Time Imbalance (100BASE-TX) 0 0.5 ns TA = 25°C 170
Duty cycle Distortion (100BASE-TX) -0.25 0.25 ns TA = 25°C 170
Overshoot (100BASE-TX) 5 % TA = 25°C 170
Output Jitter Peak-to-Peak (100BASE-TX) 0.7 1.4 ns TA = 25°C 170
Squelch Threshold (10BASE-Te) Vsq 400 mV TA = 25°C; 5MHz Square Wave 171
Peak Differential Output Voltage (10BASE-Te) Vp 1.54 1.75 1.96 V TA = 25°C; 100Ω termination on the differential output 171
Jitter Added (10BASE-Te) 3.5 ns TA = 25°C; 100Ω termination on the differential output (peak-to-peak) 171
Rise/Fall Time (10BASE-Te) tr, tf 25 ns TA = 25°C 171
AVDDH supply current (Full 1000 Mbps) IDD_AH 330 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 1000BASE-T; Ports 6 & 7 in RGMII (1000 Mbps); All ports 100% utilization 169
VDDIO supply current (Full 1000 Mbps) IDD_IO 80 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 1000BASE-T; Ports 6 & 7 in RGMII (1000 Mbps); All ports 100% utilization 169
AVDDL supply current (Full 1000 Mbps) IDD_CA 460 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 1000BASE-T; Ports 6 & 7 in RGMII (1000 Mbps); All ports 100% utilization 169
DVDDL supply current (Full 1000 Mbps) IDD_CD 750 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 1000BASE-T; Ports 6 & 7 in RGMII (1000 Mbps); All ports 100% utilization 169
AVDDH supply current (Full 100 Mbps) IDD_AH 140 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in MII (100 Mbps); All ports 100% utilization 169
VDDIO supply current (Full 100 Mbps) IDD_IO 35 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in MII (100 Mbps); All ports 100% utilization 169
AVDDL supply current (Full 100 Mbps) IDD_CA 140 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in MII (100 Mbps); All ports 100% utilization 169
DVDDL supply current (Full 100 Mbps) IDD_CD 350 mA TA = 25°C; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in MII (100 Mbps); All ports 100% utilization 169

CAD (KiCad official)

  • Symbol: KSZ9897RTXI
  • Footprint: Package_QFP:TQFP-128_14x14mm_P0.4mm
  • 3D model: TQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: ksz9897rtxi-etched.step / ksz9897rtxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9897rtxi.step / ksz9897rtxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (196 pp, sha256 72b89179ed6a42a7, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF