# JMTP3010D

**Jiangsu JieJie Microelectronics** · MOSFETs · SOP-8

JMTP3010D from Jiangsu JieJie Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S2 | passive | Source of MOSFET 2 (N-channel, 30V VDSS, 12A continuous drain current). |
| 2 | G2 | input | Gate of MOSFET 2, with gate-source voltage limited to ±20V and threshold of 1.0V to 2.5V. |
| 3 | S1 | passive | Source of MOSFET 1 (N-channel, 30V VDSS, 12A continuous drain current). |
| 4 | G1 | input | Gate of MOSFET 1, with gate-source voltage limited to ±20V and threshold of 1.0V to 2.5V. |
| 5 | D1 | passive | Drain of MOSFET 1, tied to pin 6, with 30V maximum drain-source voltage. |
| 6 | D1 | passive | Drain of MOSFET 1, tied to pin 5, with 30V maximum drain-source voltage. |
| 7 | D2 | passive | Drain of MOSFET 2, tied to pin 8, with 30V maximum drain-source voltage. |
| 8 | D2 | passive | Drain of MOSFET 2, tied to pin 7, with 30V maximum drain-source voltage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu JieJie Microelectronics |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 30 | V |  | 1 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | 12 | A | TA = 25℃ | 1 |
| Continuous Drain Current | ID |  |  | 8 | A | TA = 100℃ | 1 |
| Pulsed Drain Current | IDM |  |  | 48 | A |  | 1 |
| Single Pulsed Avalanche Energy | EAS |  |  | 16 | mJ | TJ=25℃, VGS=10V, RG=25Ω, L=0.5mH, IAS=11.5A (note 2) | 1 |
| Power Dissipation | PD |  |  | 3 | W | TA = 25℃ | 1 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 46 | ℃/W |  | 1 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | ℃ |  | 1 |
| Drain-Source Breakdown Voltage | V(BR)DSS | 30 |  |  | V | VGS=0V, ID=250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | μA | VDS=30V, VGS=0V | 2 |
| Gate to Body Leakage Current | IGSS | -100 |  | 100 | nA | VDS=0V, VGS=±20V | 2 |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VDS=VGS, ID=250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 9 | 12 | mΩ | VGS=10V, ID=12A (note 3) | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 13 | 18 | mΩ | VGS=4.5V, ID=10A (note 3) | 2 |
| Maximum Continuous Drain to Source Diode Forward Current | IS |  |  | 12 | A |  | 2 |
| Maximum Pulsed Drain to Source Diode Forward Current | ISM |  |  | 48 | A |  | 2 |
| Drain to Source Diode Forward Voltage | VSD |  |  | 1.2 | V | VGS=0V, IS=12A | 2 |

## CAD (KiCad official)

- Symbol: `JMTP3010D`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `jmtp3010d-etched.step` / `jmtp3010d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `jmtp3010d.step` / `jmtp3010d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Jiangsu JieJie Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603082815865446400) (6 pp, sha256 `e7f308388976ed24`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/jmtp3010d-datasheet.pdf)