# JCS4N80RC

**Jilin Sino Microelectronics** · MOSFETs · DPAK

JCS4N80RC from Jilin Sino Microelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; drive with VGS=10V for the stated RDS(ON), absolute maximum VGSS ±30 V, threshold 2.0 to 4.0 V at ID=250μA. |
| 2 | D | passive | Drain, connected to the exposed mounting tab; VDSS 800 V, continuous ID 4 A at 25℃ and pulsed IDM 16 A. |
| 3 | S | passive | Source; body diode continuous forward current IS 4 A and pulsed ISM 16 A to the drain. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Jilin Sino Microelectronics |
| Package | DPAK |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (breakdown) | BVDSS | 800 |  |  | V | ID=250μA, VGS=0V | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 5 | μA | VDS=800V, VGS=0V, TC=25℃ | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 100 | μA | VDS=640V, TC=125℃ | 3 |
| Gate-body leakage current, forward | IGSSF |  |  | 100 | nA | VDS=0V, VGS=30V | 3 |
| Gate-body leakage current, reverse | IGSSR |  |  | -100 | nA | VDS=0V, VGS=-30V | 3 |
| Gate Threshold Voltage | VGS(th) | 2 |  | 4 | V | VDS=VGS, ID=250μA | 3 |
| Static Drain-Source On-Resistance | RDS(ON) | 0.5 | 1.9 | 2.6 | Ω | VGS=10V, ID=2.0A, 25℃ | 3 |
| Static Drain-Source On-Resistance | RDS(ON) | 0.6 | 3.3 | 4.5 | Ω | VGS=10V, ID=2.0A, 100℃ | 3 |
| Static Drain-Source On-Resistance | RDS(ON) | 0.8 | 4.9 | 6.5 | Ω | VGS=10V, ID=2.0A, 150℃ | 3 |
| Gate resistance | Rg | 0.5 |  | 6 | Ω | F=1.0MHZ, open drain | 3 |
| Input capacitance | Ciss | 300 | 675 | 880 | pF | VDS=25V, VGS=0V, f=1.0MHZ | 3 |
| Output capacitance | Coss | 40 | 78 | 100 | pF | VDS=25V, VGS=0V, f=1.0MHZ | 3 |
| Reverse transfer capacitance | Crss | 2 | 8.8 | 15 | pF | VDS=25V, VGS=0V, f=1.0MHZ | 3 |
| Turn-On delay time | td(on) |  | 18 | 40 | ns | VDD=400V, ID=4A, RG=25Ω | 4 |
| Turn-On rise time | tr |  | 48 | 100 | ns | VDD=400V, ID=4A, RG=25Ω | 4 |
| Turn-Off delay time | td(off) |  | 39 | 80 | ns | VDD=400V, ID=4A, RG=25Ω | 4 |
| Turn-Off Fall time | tf |  | 38 | 80 | ns | VDD=400V, ID=4A, RG=25Ω | 4 |
| Total Gate Charge | Qg |  | 29.5 | 45 | nC | VDS=640V, ID=4A, VGS=10V | 4 |
| Gate-Source charge | Qgs |  | 4.8 | 12 | nC | VDS=640V, ID=4A, VGS=10V | 4 |
| Gate-Drain charge | Qgd |  | 12.8 | 30 | nC | VDS=640V, ID=4A, VGS=10V | 4 |
| Maximum Continuous Drain-Source Diode Forward Current | IS |  |  | 4 | A |  | 4 |
| Maximum Pulsed Drain-Source Diode Forward Current | ISM |  |  | 16 | A |  | 4 |
| Drain-Source Diode Forward Voltage | VSD |  |  | 1.5 | V | VGS=0V, IS=4A | 4 |
| Reverse recovery time | trr |  | 580 | 1500 | ns | VGS=0V, IS=4A, dIF/dt=100A/μs | 4 |
| Reverse recovery charge | Qrr |  | 3.8 | 9 | μC | VGS=0V, IS=4A, dIF/dt=100A/μs | 4 |
| Drain-Source Voltage | VDSS |  |  | 800 | V |  | 2 |
| Drain Current - continuous | ID |  |  | 4 | A | TC=25℃ | 2 |
| Drain Current - continuous | ID |  |  | 2.48 | A | TC=100℃ | 2 |
| Drain Current - pulse (note 1) | IDM |  |  | 16 | A | Pulse width limited by maximum junction temperature | 2 |
| Gate-Source Voltage | VGSS | -30 |  | 30 | V |  | 2 |
| Single Pulsed Avalanche Energy (note 2) | EAS |  |  | 470 | mJ | L=55mH, IAS=4A, VDD=50V, RG=25Ω, starting TJ=25℃ | 2 |
| Avalanche Current (note 1) | IAR |  |  | 4 | A |  | 2 |
| Repetitive Avalanche Energy (note 1) | EAR |  |  | 13 | mJ |  | 2 |
| Peak Diode Recovery dv/dt (note 3) | dv/dt |  |  | 4 | V/ns | ISD ≤4A, di/dt ≤200A/μs, VDD≤BVDSS, starting TJ=25℃ | 2 |
| Power Dissipation | PD |  |  | 45.8 | W | TC=25℃ | 2 |
| Power Dissipation derating | PD |  |  | 0.37 | W/℃ | Derate above 25℃ | 2 |
| Operating and Storage Temperature Range | TJ，TSTG | -55 |  | 150 | ℃ |  | 2 |
| Maximum Lead Temperature for Soldering Purposes | TL |  |  | 300 | ℃ |  | 2 |
| Thermal Resistance, Junction to Case | Rth(j-c) |  |  | 2.73 | ℃/W | JCS4N80RC (DPAK) | 4 |
| Thermal Resistance, Junction to Ambient | Rth(j-A) |  |  | 110 | ℃/W | JCS4N80RC (DPAK) | 4 |

## CAD (KiCad official)

- Symbol: `JCS4N80RC`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: DPAK (KiCad packages3D, STEP)
- 3D model files: `jcs4n80rc-etched.step` / `jcs4n80rc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `jcs4n80rc.step` / `jcs4n80rc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Jilin Sino Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590237160248287232) (13 pp, sha256 `bca451130938e03c`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/jcs4n80rc-datasheet.pdf)