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ISL81801FRTZ-T

RENESAS · DC-DC Converters · TQFN-32(5X5)

ISL81801FRTZ-T from RENESAS, in a TQFN-32(5X5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BSTEN	bidirectional	DE Burst mode enable signal, pulled up to 5V by an internal 250k resistor in PWM and DE mode and pulled low in Burst mode; tie together across chips in parallel operation.
2	FB_IN	input	Input voltage feedback for reverse direction operation, regulated to 0.8V; keep below 0.3V to disable reverse operation, or tie to VCC5V or SGND if unused to set interleave phase shift.
3	VCC5V	power_out	Output of the internal 5V linear regulator that biases the IC; must be decoupled to SGND with at least 4.7µF ceramic capacitor.
4	NC	unconnected	No connection pin.
5	RT/SYNC	input	Resistor to ground sets switching frequency from 100kHz to 600kHz (open or tied to VCC5V gives 120kHz, tied to GND gives 575kHz); also accepts an external clock for synchronization.
6	PLL_COMP	passive	Compensation pin for the internal PLL; RPLL 2.7kΩ, CPLL1 10nF and CPLL2 820pF network is recommended.
7	CLKOUT/DITHER	bidirectional	With no capacitor it outputs a clock to synchronize other ISL81801s; with a capacitor the clock out is disabled and frequency dither of ±15% is enabled.
8	SS/TRK	input	Soft-start capacitor pin charged by a regulated 2µA source, or tracking input from a master supply via a resistor divider.
9	COMP	output	Voltage error GM amplifier output that sets the inner current loop reference; duty cycle reduces to 0% when pulled below 1V.
10	FB_OUT	input	Output voltage feedback input regulated to the internal 0.8V reference via a resistive divider to SGND.
11	IMON_OUT	output	Output current monitor with current proportional to ISEN+ minus ISEN- voltage; average current limit acts at 1.2V and Burst mode threshold is about 850mV/880mV.
12	OV	bidirectional	OVP comparator signal pulled low by an internal 250k resistor in normal operation and pulled high when output OVP trips; connect together in parallel operation.
13	ISEN-	input	Output current sense signal negative input pin.
14	ISEN+	input	Output current sense signal positive input pin.
15	PGOOD	output	Open-drain power good output pulled low when output is not within ±10% of nominal or EN is low.
16	UG2	output	High-side MOSFET gate driver output controlled by the boost PWM signal.
17	PHASE2	passive	Phase node of the boost converter, connected to the junction of upper MOSFET source, inductor and lower MOSFET drain.
18	BOOT2	passive	Bootstrap pin for the boost high-side driver with a bootstrap diode to VDD; refresh pulse is issued when BOOT2-PHASE2 drops to 5.95V.
19	LG2/OC_MODE	bidirectional	Low-side boost gate driver output and OCP mode set pin; at initialization 10µA sets voltage, below 0.3V gives constant current mode and above 0.3V gives Hiccup mode.
20	VDD	power_out	Output of the internal 8V linear regulator supplied by VIN or EXTBIAS for low-side drivers and boot circuitry; decouple to PGND with at least 4.7µF.
21	PGND	power_in	Power ground connected to the sources of the lower MOSFETs and the negative terminals of the VDD decoupling capacitors.
22	LG1/PWM_MODE	bidirectional	Low-side buck gate driver output and PWM mode set pin; at initialization 10µA sets voltage, below 0.3V gives forced PWM mode and above 0.3V gives Diode Emulation mode.
23	BOOT1	passive	Bootstrap pin for the buck high-side driver with a bootstrap diode to VDD; refresh pulse is issued when BOOT1-PHASE1 drops to 5.95V.
24	PHASE1	passive	Phase node of the buck converter, connected to the junction of upper MOSFET source, inductor and lower MOSFET drain.
25	UG1	output	High-side MOSFET gate driver output controlled by the buck PWM signal.
26	EXTBIAS	power_in	External bias input for the optional VDD LDO, which disconnects the VIN LDO above 7.5V; decouple with 10µF when used, otherwise tie to ground, do not float.
27	VIN	power_in	Input rail connection through a 5-10Ω resistor powering the internal VDD LDO, decoupled with 10nF to 1µF to ground; operating range 4.5V to 80V.
28	CS+	input	Input current sense signal positive input pin.
29	CS-	input	Input current sense signal negative input pin.
30	EN/UVLO	input	Enable and accurate UVLO pin: LDOs activate at 1.3V and PWM is enabled at 1.8V, internally pulled up when floating, maximum current into pin 100µA.
31	IMON_IN	bidirectional	Input current monitor with current proportional to CS+ minus CS- voltage and average current limit at 1.2V; tie to VCC5V or SGND if unused to set interleave phase shift.
32	CLKEN	bidirectional	DE burst off-state enable signal pulled up to 5V by an internal 250k resistor and pulled low in Burst off state; tie together across chips in parallel operation.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	TQFN-32(5X5)
Category	Power Supply Chip
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage Range	VIN	4.5		80	V		13
Shutdown Current	IVINQ		2.7	6	µA	EN = 0V, PGOOD is floating	13
Operating Current	IVINOP		5	7	mA	PGOOD is floating, EXTBIAS = 0V	13
Operating Current (EXTBIAS)	IVINOP		50		µA	PGOOD is floating, EXTBIAS = 12V	13
VCC5V Internal LDO Output Voltage	VCC5V	4.7	5	5.4	V	VIN = 8V, IL = 0mA	13
Maximum Supply Current of Internal LDO (VCC5V)	IVCC_MAX	120			mA	VVCC5V = 0V, VIN = 8V	13
VDD Internal LDO Output Voltage	VDD	7.5	8	8.4	V	VIN = 12V, EXTBIAS = 0V, IL = 0mA	13
Maximum Supply Current of Internal LDO (VDD)	IVDD_MAX	120			mA	VVDD = 0V, EXTBIAS = 0V, VIN = 12V	13
Maximum Supply Current of Internal LDO (VDD, EXTBIAS)	IVDD_MAX	140			mA	VVDD = 4.5V, EXTBIAS = 12V, VIN = 4.5V	13
EXTBIAS Switch Over Threshold Voltage, Rising	VEXT_THR	7.1	7.38	7.55	V	EXTBIAS voltage	13
EXTBIAS Switch Over Threshold Voltage, Falling	VEXT_THF	6.6	6.85	7.1	V	EXTBIAS voltage	13
VIN Rising UVLO Threshold	VUVLOTHR			3.5	V	VIN voltage, 0mA on VCC5V and VDD	13
VIN Falling UVLO Threshold	VUVLOTHF	3	3.2	3.4	V	VIN voltage, 0mA on VCC5V and VDD	13
VCC5V Rising POR Threshold	VPORTHR	3.7	4	4.3	V	VCC5V voltage, 0mA on VCC5V and VDD	13
VCC5V Falling POR Threshold	VPORTHF	3.3	3.55	3.75	V	VCC5V voltage, 0mA on VCC5V and VDD	13
EN Rise Threshold	VENSS_THR	0.75	1.05	1.3	V	VIN > 5.6V	13
EN Fall Threshold	VENSS_THF	0.6	0.9	1.1	V	VIN > 5.6V	13
EN Hysteresis	VENSS_HYST	70	150	300	mV	VIN > 5.6V	13
UVLO Rise Threshold	VUVLO_THR	1.77	1.8	1.83	V	VIN > 5.6V	13
UVLO Hysteresis Current	IUVLO_HYST	2.5	4.4	6	µA	VIN = 12V, EN/UVLO = 1.815V	13
PGOOD Upper Threshold	VPGOV	107	109	112	%		14
PGOOD Lower Threshold	VPGUV	87	90	92	%		14
PGOOD Low Level Voltage	VPGLOW			0.35	V	I_SINK = 2mA	14
PGOOD Leakage Current	IPGLKG		0	150	nA	PGOOD = 5V	14
VOUT Rising Threshold to PGOOD Rising	tPGR		1.1	5	ms		14
Reference Voltage Accuracy (voltage loop)	VREFV	-0.75		0.75	%	TA = 0°C to +85°C	14
Reference Voltage Accuracy (voltage loop)	VREFV	-1		1	%	TA = -40°C to +125°C	14
Reference Voltage Accuracy (current loop)	VREFI	-0.75		0.75	%	TA = 0°C to +85°C	14
Reference Voltage Accuracy (current loop)	VREFI	-1		1	%	TA = -40°C to +125°C	14
FB_OUT Pin Bias Current	IFBOUTLKG	-50	0	50	nA		14
FB_IN Pin Bias Current	IFBINLKG	-50	0	50	nA		14
Input Current Sense Common-Mode Voltage Range	CMIRCS	0		80	V		15
IMON_IN Offset Current	ICSOFFSET	17	19.5	21.5	µA	CS+ = CS- = 12V	15
Input Current Sense Voltage to IMON_IN Current Source Gain	GmCS	170	205	230	µS	12V common-mode voltage applied to CS± pins, 0 to 40mV differential voltage	15
Output Current Sense Common-Mode Voltage Range	CMIRISEN	0		80	V		15
IMON_OUT Offset Current	IISENOFFSET	17	19.5	21	µA	ISEN+ = ISEN- = 12V	15
IMON_OUT Current		25	27.5	28.5	µA	ISEN+ = 12V. ISEN- = 11.96V	15
Output Current Sense Voltage to IMON_OUT Current Source Gain	GmISEN	170	205	235	µS	12V common-mode voltage applied to ISEN± pins, 0mV to 40mV differential voltage	15
Buck Mode Ramp Offset	VROFFSET1	0.88	1	1.11	V		15
Boost Mode Ramp Offset	VROFFSET2	2.84	3.3	3.7	V		15
Switching Frequency	fSW	220	245	265	kHz	RT = 144kΩ	15
Switching Frequency	fSW	420	450	485	kHz	RT = 72kΩ	15
Switching Frequency	fSW	90	120	145	kHz	RT Open or to VCC5V	15
Switching Frequency	fSW	470	575	650	kHz	RT = 0V	15
SYNC Synchronization Range	fSYNC	140		600	kHz		15
CLKOUT Frequency	fCLK	420	450	485	kHz	RT = 72kΩ	16
LG1/PWM_MODE Current Source	IMODELG1	7.5	10	13	µA		16
Burst Mode Enter Threshold	VIMONOUTBSTEN	0.808	0.835	0.86	V	IMON_OUT pin voltage	16
Burst Mode Exit Threshold	VMONOUTBSTEX	0.83	0.88	0.92	V	IMON_OUT pin voltage	16
Burst Mode Peak Current Limit Input Shunt Set Point	VBST-CS	16	27	39	mV	VCS+ - VCS-, 12V common-mode voltage applied to CS± pins	16
Driver 1, 2 BOOT Refresh Trip Voltage	VBOOTRF1,2	5.4	5.95	6.65	V	BOOT voltage - PHASE voltage	16
Output OVP Threshold	VOVTH_OUT	112	114	116	%		17
LG2/OC_MODE Current Source	IMODELG2	7.5	10	13	µA		17
Pulse-by-Pulse Peak Current Limit Input Shunt Set Point	VOCSET-CS	68	82	96	mV	VCS+ - VCS-, 12V common-mode voltage applied to CS± pins	17
Pulse-by-Pulse Negative Peak Current Limit Output Shunt Set Point	VOCSET-ISEN	-70	-59	-44	mV	VISEN+ - VISEN-, 12V common-mode voltage applied to ISEN± pins	17
Input Constant and Hiccup Current Limit Set Point	VIMONINCC	1.18	1.2	1.22	V	IMON_IN Pin Voltage	17
Input Constant and Hiccup Current Limit Set Point at CS± Input	VAVOCP_CS	42	51	63	mV	VCS+ - VCS-, 12V common-mode applied to CS± pins, RIMON_IN = 40.2k, TJ = -40°C to +125°C	17
Output Constant and Hiccup Current Limit Set Point	VIMONOUTCC	1.18	1.2	1.22	V	IMON_OUT Pin Voltage	17
Output Constant and Hiccup Current Limit Set Point at ISEN± Input	VAVOCP_ISEN	43	51	63	mV	VISEN+ - VISEN-, 12V common-mode applied to ISEN± pins, RIMON_OUT = 40.2k, TJ = -40°C to +125°C	17
Operating Temperature		-40		125	°C		12
Junction Temperature		-55		150	°C		12
Storage Temperature Range		-65		150	°C		12
VIN, CS+, CS-, ISEN+, ISEN- to GND		-0.3		85	V		12
VIN to GND	VIN	4.5		80	V		12
Thermal Resistance Junction to Ambient, 32 Ld TQFN	θJA		29		°C/W	Notes 4, 5	12
Thermal Resistance Junction to Case, 32 Ld TQFN	θJC		1		°C/W	Notes 4, 5	12

CAD (KiCad official)

Symbol: ISL81801FRTZ-T
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: TQFN-32(5X5) (KiCad packages3D, STEP)
3D model files: isl81801frtz-t-etched.step / isl81801frtz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl81801frtz-t.step / isl81801frtz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (50 pp, sha256 e51f11fea5d82478, retrieved 2026-10-23, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF