# ISL81601FRZ-T

**RENESAS** · DC-DC Controllers · QFN-32(5x5)

ISL81601FRZ-T from RENESAS, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BSTEN | bidirectional | Burst mode enable: pulled up to 5V through an internal 250k resistor in PWM and DE mode, pulled low (rDS(ON) about 4.5k) in Burst mode; tie together in multi-chip parallel operation. |
| 2 | FB_IN | input | Input voltage feedback for reverse-direction operation, regulated to 0.8V; keep below 0.3V to disable reverse operation, and tie to VCC5V or SGND when unused to set interleaving phase. Rated 0 to 5.25V. |
| 3 | VCC5V | power_out | Output of the internal 5V linear regulator that biases the IC; must be decoupled to SGND with at least 4.7µF ceramic placed very close to the pin. |
| 4 | NC | unconnected | No connection pin. |
| 5 | RT/SYNC | input | Resistor to ground sets the default switching frequency from 100kHz to 600kHz per Equation 1; open or tied to VCC5V gives 120kHz, tied to GND gives 575kHz, and an external clock applied here synchronizes the internal oscillator. |
| 6 | PLL_COMP | passive | PLL compensation pin requiring the RPLL/CPLL1/CPLL2 network, with 2.7kΩ, 10nF and 820pF recommended, to keep PLL stability across 100kHz to 600kHz. |
| 7 | CLKOUT/DITHER | bidirectional | Clock output that synchronizes other ISL81601s when no capacitor is connected; a capacitor here disables clock out and enables ±15% frequency dithering before soft-start. |
| 8 | SS/TRK | passive | Soft-start capacitor pin charged by a regulated 2µA current to set the output ramp, or a tracking input fed from a master rail through a resistor divider. |
| 9 | COMP | passive | Voltage error GM amplifier output that sets the inner current-loop reference, with the compensation network connected between COMP and SGND; the PWM duty cycle falls to 0% when COMP is pulled below 1V. |
| 10 | FB_OUT | input | Output voltage feedback input, connected to a resistive divider between VOUT and SGND, regulated to the internal 0.8V reference. |
| 11 | IMON_OUT | output | Output current monitor whose voltage is proportional to average output current; reaching 1.2V activates the average current limit, and Burst mode is entered below 850mV and exited above 880mV. |
| 12 | OV | bidirectional | OVP comparator output, pulled low through 250k in normal operation and pulled high when output OVP trips (threshold 112% to 116% of nominal); tie together in parallel operation. |
| 13 | ISEN- | input | Output current sense negative input, with ISEN+ forming the differential sense across the output sense resistor. |
| 14 | ISEN+ | input | Output current sense positive input, with ISEN- forming the differential sense across the output sense resistor. |
| 15 | PGOOD | output | Open-drain power-good output that is pulled low when VOUT is outside ±10% of nominal or when EN is pulled low. |
| 16 | UG2 | output | High-side MOSFET gate driver output for the boost converter, controlled by the boost PWM signal. |
| 17 | PHASE2 | passive | Boost converter phase node at the junction of the upper MOSFET source, filter inductor and lower MOSFET drain; rated -5V (<20ns) / -0.3V DC to +70V to GND. |
| 18 | BOOT2 | passive | Bootstrap pin for the boost high-side driver, connected to VDD through a bootstrap diode; the BOOT2-to-PHASE2 voltage is refreshed when it falls to 5.95V typical (5.4V to 6.65V). |
| 19 | LG2/OC_MODE | output | Boost low-side gate driver output controlled by the boost PWM signal, and an OCP mode set pin where a resistor to ground selects constant-current OCP below 0.3V or hiccup OCP above 0.3V (sourced 10µA at initiation). |
| 20 | VDD | power_out | Output of the internal 8V linear regulator supplied from VIN or EXTBIAS that biases the low-side drivers and bootstrap circuits; must be decoupled to PGND with at least 4.7µF ceramic placed very close to the pin, and is rated 0 to 8.3V. |
| 21 | PGND | power_in | Power ground connected to the lower MOSFET sources and the negative terminals of the VDD decoupling capacitors. |
| 22 | LG1/PWM_MODE | output | Buck low-side gate driver output controlled by the buck PWM signal, and a PWM mode set pin where a resistor to ground selects forced PWM below 0.3V or DE mode above 0.3V (sourced 10µA at initiation). |
| 23 | BOOT1 | passive | Bootstrap pin for the buck high-side driver, connected to VDD through a bootstrap diode; the BOOT1-to-PHASE1 voltage is refreshed when it falls to 5.95V typical (5.4V to 6.65V). |
| 24 | PHASE1 | passive | Buck converter phase node at the junction of the upper MOSFET source, filter inductor and lower MOSFET drain; rated -5V (<20ns) / -0.3V DC to +70V to GND. |
| 25 | UG1 | output | High-side MOSFET gate driver output for the buck converter, controlled by the buck PWM signal. |
| 26 | EXTBIAS | power_in | External bias input for the optional VDD LDO, with an internal switch disconnecting the VIN LDO above 7.5V; rated 0 to 36V, decoupled with 10µF when used, and must not be left floating (tie to ground when unused). |
| 27 | VIN | power_in | Input rail, tied through a 5 to 10Ω resistor, that powers the internal VDD LDO and is rated 4.5V to 60V; decouple to ground with a 10nF to 1µF ceramic. |
| 28 | CS+ | input | Input current sense positive input, with CS- forming the differential input-current sense across the input sense resistor. |
| 29 | CS- | input | Input current sense negative input, with CS+ forming the differential input-current sense across the input sense resistor. |
| 30 | EN/UVLO | input | Enable and accurate UVLO pin that disables the output when grounded, activates the VDD and VCC5V LDOs at 1.3V and enables the PWM modulator at 1.8V; floating enables the part through an internal pull-up, and it is rated 0 to 5.25V. |
| 31 | IMON_IN | input | Input current monitor whose voltage is proportional to average input current; reaching 1.2V activates the input current limit, and it is tied to VCC5V or SGND when unused to set interleaving phase. |
| 32 | CLKEN | bidirectional | DE mode burst-off enable, pulled up to 5V through 250k in PWM, DE and burst-on states and pulled low in the burst-off state (rDS(ON) about 4.5k); tie together in multi-chip parallel operation. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | QFN-32(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC5V, EN/UVLO, FB_IN to GND |  | -0.3 |  | 5.9 | V |  | 13 |
| VDD to GND |  | -0.3 |  | 9 | V |  | 13 |
| EXTBIAS to GND |  | -0.3 |  | 40 | V |  | 13 |
| VIN, CS+, CS-, ISEN+, ISEN- to GND |  | -0.3 |  | 70 | V |  | 13 |
| BOOT1, 2/UG1, 2 to PHASE1, 2 (max printed as VDD + 0.3) |  | -0.3 |  |  | V |  | 13 |
| PHASE1, 2 to GND (transient) |  | -5 |  | 70 | V | <20 ns | 13 |
| PHASE1, 2 to GND (DC) |  | -0.3 |  | 70 | V | DC | 13 |
| FB_OUT, SS/TRK, COMP, RT/SYNC, PLL_COMP, CLKOUT/DITHER, BSTEN, CLKEN, OV, PGOOD, IMON_IN, IMON_OUT to GND (max printed as VCC5V + 0.3) |  | -0.3 |  |  | V |  | 13 |
| LG1/PWM_MODE, LG2/OC_MODE to GND (max printed as VDD + 0.3) |  | -0.3 |  |  | V |  | 13 |
| CS+ to CS- and ISEN+ to ISEN- |  | -0.3 |  | 0.3 | V |  | 13 |
| VCC5V, VDD short-circuit to GND duration |  |  |  | 1 | s | short-circuit to GND | 13 |
| ESD Human Body Model |  |  |  | 2 | kV | Tested per JS-001-2017 | 13 |
| ESD Machine Model |  |  |  | 150 | V | Tested per JESD22-A115C | 13 |
| ESD Charge Device Model |  |  |  | 1.5 | kV | Tested per JS-002-2014 | 13 |
| Latch-Up |  |  |  | 100 | mA | Tested per JESD78E; Class II, Level A, +125°C (TJ) | 13 |
| Junction Temperature | TJ | -55 |  | 150 | °C |  | 13 |
| Operating Temperature |  | -40 |  | 125 | °C |  | 13 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 13 |
| Temperature |  | -40 |  | 125 | °C |  | 14 |
| VIN to GND | VIN | 4.5 |  | 60 | V |  | 14 |
| VCC5V, EN/UVLO, FB_IN to GND |  | 0 |  | 5.25 | V |  | 14 |
| VDD to GND | VDD | 0 |  | 8.3 | V |  | 14 |
| EXTBIAS to GND |  | 0 |  | 36 | V |  | 14 |
| Shutdown Current | IVINQ |  | 2.7 | 6 | µA | EN = 0V, PGOOD is floating | 14 |
| Operating Current | IVINOP |  | 4.7 | 6 | mA | PGOOD is floating | 14 |
| Internal LDO Output Voltage VCC5V | VCC5V | 4.7 | 5.1 | 5.25 | V | VIN = 8V, IL = 0mA | 14 |
| Maximum Supply Current of Internal LDO (VCC5V) | IVCC_MAX |  |  | 120 | mA | VVCC5V = 0V, VIN = 8V | 14 |
| Internal LDO Output Voltage VDD | VDD | 7.5 | 8 | 8.3 | V | VIN = 12V, EXTBIAS = 0V, IL = 0mA | 14 |
| Internal LDO Output Voltage VDD | VDD | 7.6 | 8 | 8.3 | V | VIN = 60V, EXTBIAS = 12V, IL = 0mA | 14 |
| Internal LDO Output Voltage VDD | VDD | 7.3 |  | 7.85 | V | VIN > 8.6V, EXTBIAS = 0V, IL = 75mA | 14 |
| Maximum Supply Current of Internal LDO (VDD) | IVDD_MAX |  |  | 120 | mA | VVDD = 0V, EXTBIAS = 0V, VIN = 12V | 14 |
| EXTBIAS Switch Over Threshold Voltage, Rising | VEXT_THR | 7.1 | 7.38 | 7.55 | V | EXTBIAS voltage | 14 |
| VIN Rising UVLO Threshold | VUVLOTHR | 3.2 | 3.5 | 3.85 | V | VIN voltage, 0mA on VCC5V and VDD | 15 |
| VIN Falling UVLO Threshold | VUVLOTHF | 3 | 3.2 | 3.4 | V | VIN voltage, 0mA on VCC5V and VDD | 15 |
| VCC5V Rising POR Threshold | VPORTHR | 3.7 | 4 | 4.3 | V | VCC5V voltage, 0mA on VCC5V and VDD | 15 |
| VCC5V Falling POR Threshold | VPORTHF | 3.3 | 3.55 | 3.75 | V | VCC5V voltage, 0mA on VCC5V and VDD | 15 |
| EN Rise Threshold | VENSS_THR | 0.75 | 1.05 | 1.3 | V | VIN > 5.6V | 15 |
| EN Fall Threshold | VENSS_THF | 0.6 | 0.9 | 1.1 | V | VIN > 5.6V | 15 |
| UVLO Rise Threshold | VUVLO_THR | 1.77 | 1.8 | 1.83 | V | VIN > 5.6V | 15 |
| PGOOD Upper Threshold | VPGOV | 107 | 109 | 112 | % |  | 15 |
| PGOOD Lower Threshold | VPGUV | 87 | 90 | 92 | % |  | 15 |
| Reference Voltage Accuracy (internal voltage loop) | VREFV | -0.75 |  | 0.75 | % | TA = 0°C to +85°C | 15 |
| Reference Voltage Accuracy (internal voltage loop) | VREFV | -1 |  | 1 | % | TA = -40°C to +125°C | 15 |
| Buck Mode Ramp Offset | VROFFSET1 | 0.88 | 0.95 | 1.11 | V |  | 16 |
| Boost Mode Ramp Offset | VROFFSET2 | 2.84 | 3.15 | 3.7 | V |  | 16 |
| IMON_IN Offset Current | ICSOFFSET | 15.5 | 19.5 | 22.5 | µA | CS+ = CS- = 12V | 16 |
| Input Current Sense Voltage to IMON_IN Current Source Gain | GmCS | 170 | 200 | 220 | µS | 12V common-mode voltage applied to CS+/- pins, 0 to 40mV differential voltage | 16 |
| Switching Frequency | fSW | 220 | 245 | 265 | kHz | RT = 144kΩ | 17 |
| Switching Frequency | fSW | 420 | 450 | 485 | kHz | RT = 72kΩ | 17 |
| Switching Frequency | fSW | 470 | 575 | 650 | kHz | RT = 0V | 17 |
| Pulse-by-Pulse Peak Current Limit Input Shunt Set Point | VOCSET-CS | 68 | 82 | 96 | mV | VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins | 18 |
| Pulse-by-Pulse Negative Peak Current Limit Output Shunt Set Point | VOCSET-ISEN | -72 | -59 | -48 | mV | VISEN+ - VISEN-, 12V common-mode voltage applied to ISEN+/- pins | 18 |
| Output Current Limit Input Constant and Hiccup Set Point (IMON_IN Pin Voltage) | VIMONINCC | 1.18 | 1.2 | 1.22 | V | IMON_IN Pin Voltage | 19 |
| Output OVP Threshold | VOVTH_OUT | 112 | 114 | 116 | % |  | 18 |
| SYNC Input Logic High | VSYNCH | 3.2 |  |  | V |  | 17 |
| BSTEN Input Logic High | VBSTEN-IH | 3.2 |  |  | V |  | 18 |
| Thermal Resistance, junction to ambient (32 Ld QFN) | θJA |  | 29 |  | °C/W | Measured in free air, high-effective thermal conductivity test board (Note 4) | 13 |
| Thermal Resistance, junction to case (32 Ld QFN) | θJC |  | 1.2 |  | °C/W | Case temp at center of exposed metal pad (Note 5) | 13 |

## CAD (KiCad official)

- Symbol: `ISL81601FRZ-T`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `isl81601frz-t-etched.step` / `isl81601frz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl81601frz-t.step` / `isl81601frz-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835268057563136) (54 pp, sha256 `b65ecd801c59f74f`, retrieved 2026-10-25, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl81601frz-t-datasheet.pdf)