ISL62771HRTZ

{
  "slug": "isl62771hrtz",
  "version": "0.1.0",
  "type": "component",
  "description": "RENESAS Power Management - Specialized, TQFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "isl62771hrtz",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "isl62771hrtz.kicad_sym",
    "isl62771hrtz.kicad_mod",
    "isl62771hrtz.glb",
    "isl62771hrtz.step",
    "isl62771hrtz.lbr",
    "docs/hero.png",
    "docs/isl62771hrtz-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "isl62771hrtz-hero.glb",
    "isl62771hrtz-hero.overlay.json",
    "isl62771hrtz-etched.glb"
  ],
  "component": {
    "mpn": "ISL62771HRTZ",
    "manufacturer": "RENESAS",
    "package": "TQFN-40(5x5)",
    "pin_count": 41,
    "category": "Power Management (PMIC)",
    "subcategory": "Power Management - Specialized",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9d254fb741104937f520f022f8d809a3.pdf",
    "parts": {
      "symbol": "isl62771hrtz.kicad_sym",
      "footprint": "isl62771hrtz.kicad_mod",
      "model_3d": "isl62771hrtz-hero.glb",
      "model_3d_plain": "isl62771hrtz-etched.glb",
      "model_3d_step": "isl62771hrtz-etched.step",
      "model_3d_step_plain": "isl62771hrtz.step",
      "lbr": "isl62771hrtz.lbr"
    },
    "distributor_links": {
      "lcsc": "C17654673",
      "digikey": "ISL62771HRTZ-ND",
      "mouser": "968-ISL62771HRTZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T22:54:12Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ISL62771HRTZ-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "968-ISL62771HRTZ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "NTC_NB",
        "type": "input",
        "description": "Thermistor input to the VR_HOT_L circuit that monitors Northbridge VR temperature."
      },
      {
        "number": "2",
        "name": "IMON_NB",
        "type": "output",
        "description": "Northbridge output current monitor; a current proportional to the Northbridge VR output current is sourced from this pin."
      },
      {
        "number": "3",
        "name": "SVC",
        "type": "input",
        "description": "Serial VID clock input from the CPU processor master device."
      },
      {
        "number": "4",
        "name": "VR_HOT_L",
        "type": "output",
        "description": "Thermal indicator signal to the AMD CPU; thermal overload open-drain output, active LOW."
      },
      {
        "number": "5",
        "name": "SVD",
        "type": "bidirectional",
        "description": "Serial VID data bidirectional signal between the CPU processor master device and the VR."
      },
      {
        "number": "6",
        "name": "VDDIO",
        "type": "power_in",
        "description": "Processor memory interface power rail; this pin serves as the reference to the controller IC for the processor I/O signal level."
      },
      {
        "number": "7",
        "name": "SVT",
        "type": "output",
        "description": "Serial VID Telemetry data line from the controller IC to the CPU, which also provides the telemetry and VID-on-the-fly complete signal."
      },
      {
        "number": "8",
        "name": "ENABLE",
        "type": "input",
        "description": "Enable input; a high logic level on this pin enables both VRs."
      },
      {
        "number": "9",
        "name": "PWROK",
        "type": "input",
        "description": "System power-good input; when high the SVI 2 interface is active, and this pin must be low before the ISL62771 PGOOD output goes high."
      },
      {
        "number": "10",
        "name": "IMON",
        "type": "output",
        "description": "Core output current monitor; a current proportional to the Core VR output current is sourced from this pin."
      },
      {
        "number": "11",
        "name": "NTC",
        "type": "input",
        "description": "Thermistor input to the VR_HOT_L circuit that monitors Core VR temperature."
      },
      {
        "number": "12",
        "name": "ISEN2",
        "type": "input",
        "description": "Individual current sensing for Channel 2 of the Core VR; pulling ISEN2 to +5V disables Channel 2 and the Core VR runs in single-phase mode."
      },
      {
        "number": "13",
        "name": "ISEN1",
        "type": "input",
        "description": "Individual current sensing for Channel 1 of the Core VR; if ISEN2 is tied to +5V this pin cannot be left open and must be tied to GND with a 10kΩ resistor, and if ISEN1 is tied to +5V the Core portion of the IC is shut down."
      },
      {
        "number": "14",
        "name": "ISUMP",
        "type": "input",
        "description": "Noninverting input of the transconductance amplifier for current monitor and load line of the Core output."
      },
      {
        "number": "15",
        "name": "ISUMN",
        "type": "input",
        "description": "Inverting input of the transconductance amplifier for current monitor and load line of the Core output."
      },
      {
        "number": "16",
        "name": "VSEN",
        "type": "input",
        "description": "Output voltage sense pin for the Core controller; connect to the +sense pin of the microprocessor die."
      },
      {
        "number": "17",
        "name": "RTN",
        "type": "input",
        "description": "Output voltage sense return pin for both the Core VR and Northbridge VR; connect to the -sense pin of the microprocessor die."
      },
      {
        "number": "18",
        "name": "FB",
        "type": "input",
        "description": "Output voltage feedback to the inverting input of the Core controller error amplifier."
      },
      {
        "number": "19",
        "name": "COMP",
        "type": "output",
        "description": "Core controller error amplifier output; a resistor from COMP to GND sets the Core VR offset voltage."
      },
      {
        "number": "20",
        "name": "PGOOD",
        "type": "output",
        "description": "Open-drain output indicating the Core portion of the IC is ready to supply regulated voltage; pull up externally to VDD or 3.3V through a resistor."
      },
      {
        "number": "21",
        "name": "BOOT1",
        "type": "passive",
        "description": "Connect an MLCC capacitor across BOOT1 and PHASE1; the boot capacitor is charged through an internal boot diode from VDDP each time PHASE1 drops below VDDP minus the diode drop."
      },
      {
        "number": "22",
        "name": "UGATE1",
        "type": "output",
        "description": "Output of the Phase 1 high-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 1 high-side MOSFET(s)."
      },
      {
        "number": "23",
        "name": "PHASE1",
        "type": "passive",
        "description": "Current return path for the Phase 1 high-side MOSFET gate driver of VR1; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Phase 1 output inductor."
      },
      {
        "number": "24",
        "name": "LGATE1",
        "type": "output",
        "description": "Output of the Phase 1 low-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 1 low-side MOSFET(s)."
      },
      {
        "number": "25",
        "name": "VDD",
        "type": "power_in",
        "description": "5V bias power; use a resistor [2Ω] and a decoupling capacitor from the +5V supply, with a high quality X7R MLCC recommended."
      },
      {
        "number": "26",
        "name": "VDDP",
        "type": "power_in",
        "description": "Input voltage bias for the internal gate drivers; connect +5V to this pin and decouple with at least 1µF of capacitance to GND."
      },
      {
        "number": "27",
        "name": "LGATE2",
        "type": "output",
        "description": "Output of the Phase 2 low-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 2 low-side MOSFET(s)."
      },
      {
        "number": "28",
        "name": "PHASE2",
        "type": "passive",
        "description": "Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Phase 2 output inductor."
      },
      {
        "number": "29",
        "name": "UGATE2",
        "type": "output",
        "description": "Output of the Phase 2 high-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 2 high-side MOSFET(s)."
      },
      {
        "number": "30",
        "name": "BOOT2",
        "type": "passive",
        "description": "Connect an MLCC capacitor across BOOT2 and PHASE2; the boot capacitor is charged through an internal boot diode from VDDP each time PHASE2 drops below VDDP minus the diode drop."
      },
      {
        "number": "31",
        "name": "BOOT_NB",
        "type": "passive",
        "description": "Boot connection of the Northbridge VR; connect an MLCC capacitor across BOOT_NB and PHASE_NB, charged through an internal boot diode from VDDP."
      },
      {
        "number": "32",
        "name": "UGATE_NB",
        "type": "output",
        "description": "High-side MOSFET gate driver output of the Northbridge VR; connect to the gate of the Northbridge high-side MOSFET(s)."
      },
      {
        "number": "33",
        "name": "PHASE_NB",
        "type": "passive",
        "description": "Phase connection of the Northbridge VR and current return path for the high-side gate driver; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Northbridge output inductor."
      },
      {
        "number": "34",
        "name": "LGATE_NB",
        "type": "output",
        "description": "Low-side MOSFET gate driver output of the Northbridge VR; connect to the gate of the Northbridge low-side MOSFET(s)."
      },
      {
        "number": "35",
        "name": "PGOOD_NB",
        "type": "output",
        "description": "Open-drain output indicating the Northbridge portion of the IC is ready to supply regulated voltage; pull up externally to VDDP or 3.3V through a resistor."
      },
      {
        "number": "36",
        "name": "COMP_NB",
        "type": "output",
        "description": "Northbridge VR error amplifier output; a resistor from COMP_NB to GND sets the Northbridge VR offset voltage and the switching frequency for both VRs."
      },
      {
        "number": "37",
        "name": "FB_NB",
        "type": "input",
        "description": "Output voltage feedback to the inverting input of the Northbridge controller error amplifier."
      },
      {
        "number": "38",
        "name": "VSEN_NB",
        "type": "input",
        "description": "Output voltage sense pin for the Northbridge controller; connect to the +sense pin of the microprocessor die."
      },
      {
        "number": "39",
        "name": "ISUMN_NB",
        "type": "input",
        "description": "Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR."
      },
      {
        "number": "40",
        "name": "ISUMP_NB",
        "type": "input",
        "description": "Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR."
      },
      {
        "number": "41",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed GND bottom pad is listed in the datasheet as a signal common connection without a number"
        ],
        "pages_sent": 11,
        "cost_usd": 0.0366,
        "at": "2026-10-30T22:54:03"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/9d254fb741104937f520f022f8d809a3.pdf",
        "pages": 35,
        "sha256": "8947ca125f369189",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "isl62771hrtz.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8f37bc7a9aab4742c34f137d9822c0352acc227532830034555744338483cdfc",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "isl62771hrtz-etched.step",
        "role": "eda",
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        "sha256": "771f1869f3a5f2e2c94ad91c8e7fc2707ec05665bed90afbe4cc20092b580783",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}