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RENESAS Power Management - Specialized, TQFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

component power management (pmic)isl62771hrtz factory-2.0.0 extractor-text

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ISL62771HRTZ

RENESAS · Power Management - Specialized · TQFN-40(5x5)

ISL62771HRTZ from RENESAS, in a TQFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NTC_NB	input	Thermistor input to the VR_HOT_L circuit that monitors Northbridge VR temperature.
2	IMON_NB	output	Northbridge output current monitor; a current proportional to the Northbridge VR output current is sourced from this pin.
3	SVC	input	Serial VID clock input from the CPU processor master device.
4	VR_HOT_L	output	Thermal indicator signal to the AMD CPU; thermal overload open-drain output, active LOW.
5	SVD	bidirectional	Serial VID data bidirectional signal between the CPU processor master device and the VR.
6	VDDIO	power_in	Processor memory interface power rail; this pin serves as the reference to the controller IC for the processor I/O signal level.
7	SVT	output	Serial VID Telemetry data line from the controller IC to the CPU, which also provides the telemetry and VID-on-the-fly complete signal.
8	ENABLE	input	Enable input; a high logic level on this pin enables both VRs.
9	PWROK	input	System power-good input; when high the SVI 2 interface is active, and this pin must be low before the ISL62771 PGOOD output goes high.
10	IMON	output	Core output current monitor; a current proportional to the Core VR output current is sourced from this pin.
11	NTC	input	Thermistor input to the VR_HOT_L circuit that monitors Core VR temperature.
12	ISEN2	input	Individual current sensing for Channel 2 of the Core VR; pulling ISEN2 to +5V disables Channel 2 and the Core VR runs in single-phase mode.
13	ISEN1	input	Individual current sensing for Channel 1 of the Core VR; if ISEN2 is tied to +5V this pin cannot be left open and must be tied to GND with a 10kΩ resistor, and if ISEN1 is tied to +5V the Core portion of the IC is shut down.
14	ISUMP	input	Noninverting input of the transconductance amplifier for current monitor and load line of the Core output.
15	ISUMN	input	Inverting input of the transconductance amplifier for current monitor and load line of the Core output.
16	VSEN	input	Output voltage sense pin for the Core controller; connect to the +sense pin of the microprocessor die.
17	RTN	input	Output voltage sense return pin for both the Core VR and Northbridge VR; connect to the -sense pin of the microprocessor die.
18	FB	input	Output voltage feedback to the inverting input of the Core controller error amplifier.
19	COMP	output	Core controller error amplifier output; a resistor from COMP to GND sets the Core VR offset voltage.
20	PGOOD	output	Open-drain output indicating the Core portion of the IC is ready to supply regulated voltage; pull up externally to VDD or 3.3V through a resistor.
21	BOOT1	passive	Connect an MLCC capacitor across BOOT1 and PHASE1; the boot capacitor is charged through an internal boot diode from VDDP each time PHASE1 drops below VDDP minus the diode drop.
22	UGATE1	output	Output of the Phase 1 high-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 1 high-side MOSFET(s).
23	PHASE1	passive	Current return path for the Phase 1 high-side MOSFET gate driver of VR1; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Phase 1 output inductor.
24	LGATE1	output	Output of the Phase 1 low-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 1 low-side MOSFET(s).
25	VDD	power_in	5V bias power; use a resistor [2Ω] and a decoupling capacitor from the +5V supply, with a high quality X7R MLCC recommended.
26	VDDP	power_in	Input voltage bias for the internal gate drivers; connect +5V to this pin and decouple with at least 1µF of capacitance to GND.
27	LGATE2	output	Output of the Phase 2 low-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 2 low-side MOSFET(s).
28	PHASE2	passive	Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Phase 2 output inductor.
29	UGATE2	output	Output of the Phase 2 high-side MOSFET gate driver of the Core VR; connect to the gate of the Phase 2 high-side MOSFET(s).
30	BOOT2	passive	Connect an MLCC capacitor across BOOT2 and PHASE2; the boot capacitor is charged through an internal boot diode from VDDP each time PHASE2 drops below VDDP minus the diode drop.
31	BOOT_NB	passive	Boot connection of the Northbridge VR; connect an MLCC capacitor across BOOT_NB and PHASE_NB, charged through an internal boot diode from VDDP.
32	UGATE_NB	output	High-side MOSFET gate driver output of the Northbridge VR; connect to the gate of the Northbridge high-side MOSFET(s).
33	PHASE_NB	passive	Phase connection of the Northbridge VR and current return path for the high-side gate driver; connect to the node of the high-side MOSFET source, low-side MOSFET drain and Northbridge output inductor.
34	LGATE_NB	output	Low-side MOSFET gate driver output of the Northbridge VR; connect to the gate of the Northbridge low-side MOSFET(s).
35	PGOOD_NB	output	Open-drain output indicating the Northbridge portion of the IC is ready to supply regulated voltage; pull up externally to VDDP or 3.3V through a resistor.
36	COMP_NB	output	Northbridge VR error amplifier output; a resistor from COMP_NB to GND sets the Northbridge VR offset voltage and the switching frequency for both VRs.
37	FB_NB	input	Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
38	VSEN_NB	input	Output voltage sense pin for the Northbridge controller; connect to the +sense pin of the microprocessor die.
39	ISUMN_NB	input	Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
40	ISUMP_NB	input	Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	TQFN-40(5x5)
Category	Power Management (PMIC)
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VDD, VDDP	VDD	-0.3		7	V		10
Battery Voltage	VIN			28	V		10
Boot Voltage	BOOT	-0.3		33	V		10
Boot to Phase Voltage	BOOT-PHASE	-0.3		7	V	DC	10
Boot to Phase Voltage	BOOT-PHASE	-0.3		9	V	<10ns	10
Phase Voltage	PHASE	-7			V	<20ns Pulse Width, 10µJ	10
LGATE Voltage	LGATE	-2.5			V	<20ns Pulse Width, 5µJ	10
Open-Drain Outputs PGOOD, PGOOD_NB, VR_HOT_L		-0.3		7	V		10
Maximum Junction Temperature	TJ			150	°C		10
Maximum Storage Temperature Range	TSTG	-65		150	°C		10
Thermal Resistance Junction to Ambient, 40 Ld TQFN	θJA		33		°C/W	Typical, free air, Notes 4, 5	10
Thermal Resistance Junction to Case, 40 Ld TQFN	θJC		3		°C/W	Typical, Notes 4, 5	10
Supply Voltage VDD tolerance	VDD	-5		5	%	Nominal +5V ±5%	10
Battery Voltage	VIN	4.5		25	V		10
Ambient Temperature HRTZ	TA	-10		100	°C	HRTZ	10
Junction Temperature HRTZ	TJ	-10		125	°C	HRTZ	10
+5V Supply Current	IVDD		8	11	mA	ENABLE = 1V	10
+5V Supply Current	IVDD			1	µA	ENABLE = 0V	10
VDD POR Threshold rising	VDD_PORr	4.35		4.5	V	VDD rising	10
VDD POR Threshold falling	VDD_PORf	4		4.15	V	VDD falling	10
System Accuracy HRTZ %Error (VOUT)		-0.5		0.5	%	No load; closed loop, active mode range, VID = 0.75V to 1.55V	10
System Accuracy HRTZ Error (VOUT)		-10		10	mV	No load; closed loop, active mode range, VID = 0.25V to 0.74375V	10
Maximum Output Voltage	VOUT(max)			1.55	V	VID = [00000000]	10
Minimum Output Voltage	VOUT(min)	0			V	VID = [11111111]	10
Nominal Channel Frequency	fSW(nom)	280	300	320	kHz		10
Current-Sense Amplifier Input Offset HRTZ		-0.15		0.15	mV	IFB = 0A	10
Error Amp DC Gain	Av0		119		dB		10
Error Amp Gain-Bandwidth Product	GBW		17		MHz	CL = 20pF	10
PGOOD Low Voltage	VOL			0.4	V	IPGOOD = 4mA	11
PGOOD Leakage Current	IOH	-1		1	µA	PGOOD = 3.3V	11
PWROK High Threshold			750		mV		11
VR_HOT_L Pull-Down			11		Ω		11
UGATE Pull-Up Resistance	RUGPU		1	1.5	Ω	200mA source current	11
UGATE Source Current	IUGSRC		2		A	UGATE - PHASE = 2.5V	11
UGATE Sink Resistance	RUGPD		1	1.5	Ω	250mA sink current	11
UGATE Sink Current	IUGSNK		2		A	UGATE - PHASE = 2.5V	11
LGATE Pull-Up Resistance	RLGPU		1	1.5	Ω	250mA source current	11
LGATE Source Current	ILGSRC		2		A	LGATE - VSSP = 2.5V	11
LGATE Sink Resistance	RLGPD		0.5	0.9	Ω	250mA sink current	11
LGATE Sink Current	ILGSNK		4		A	LGATE - VSSP = 2.5V	11
UGATE to LGATE Dead Time	tUGFLGR		23		ns	UGATE falling to LGATE rising, no load	11
Overvoltage Threshold	OVH	275	325	375	mV	VSEN rising above setpoint for >1µs	11
Undervoltage Threshold	OVH	275	325	375	mV	VSEN falls below setpoint for >1µs	11
Current Imbalance Threshold			9		mV	One ISEN above another ISEN for >1.2ms	11
Way Overcurrent Trip Threshold [IMONx Current Based Detection]	IMONxWOC		15		µA	All states, IDROOP = 60µA, RIMON = 135kΩ	11
Overcurrent Trip Threshold [IMONx Voltage Based Detection]	VIMONx_OCP	1.485	1.51	1.535	V	All states, IDROOP = 45µA, IIMONx = 11.25µA, RIMON = 135kΩ	11
ENABLE Input Low	VIL			1	V		11
ENABLE Input High HRTZ	VIH	1.6			V	HRTZ	11
ENABLE Leakage Current	IENABLE	-1	0	1	µA	ENABLE = 0V	11
ENABLE Leakage Current	IENABLE	18		35	µA	ENABLE = 1V	11
SVC, SVD Input Low	VIL			30	% of VDDIO		11
SVC, SVD Input High	VIH	70			% of VDDIO		11
SVC, SVD Leakage		-1		1	µA	ENABLE = 0V, SVC, SVD = 0V and 1V	11
SVC, SVD Leakage		-35	-20	-5	µA	ENABLE = 1V, SVC, SVD = 0V	11
NTC Source Current		27	30	33	µA	NTC = 0.6V	11
NTC Thermal Warning Voltage		600	640	680	mV		11
NTC Thermal Shutdown Voltage		530	580	630	mV		11
VID-on-the-Fly Slew Rate		8	10	12	mV/µs		12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for	32

CAD (KiCad official)

Symbol: ISL62771HRTZ
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: TQFN-40(5x5) (KiCad packages3D, STEP)
3D model files: isl62771hrtz-etched.step / isl62771hrtz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl62771hrtz.step / isl62771hrtz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (35 pp, sha256 8947ca125f369189, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ISL62771HRTZ

Verified ISL62771HRTZ

Verification log 1 record

ISL62771HRTZ

Pinout

Key specifications

Electrical characteristics

Materials and finish

CAD (KiCad official)

Provenance