component
ISL1208IB8Z
Public Made by Adomby adom
RENESAS Real-Time Clocks(RTC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "ISL1208IB8Z",
"brief": "RENESAS Real-Time Clocks(RTC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
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{
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{
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{
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{
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"type": "output",
"description": "Multi-function open-drain active-low pin used as interrupt output or frequency output, with the function set via the configuration register."
},
{
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"extractor flagged: The SOIC pin-number diagram on page 3 is scrambled in the extracted text, so the pin assignments wer; Pin 7 is labelled IRQ/FOUT in the datasheet with a shared function; the type is set to output based ; The datasheet gives a VDD supply range of 2.0V to 5.5V on page 8 and 2.7V to 5.5V in the DC table on"
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"name": "IRQ/FOUT output low voltage",
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{
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{
"name": "SCL falling edge to SDA output data valid",
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"source": "datasheet"
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{
"name": "Bus free time before new transmission",
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"min": 1300,
"typ": null,
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"conditions": "SDA crossing 70% of VDD during STOP, to SDA crossing 70% of VDD during following START.",
"source_page": 5,
"source": "datasheet"
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{
"name": "Clock LOW time",
"symbol": "tLOW",
"kind": "timing",
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"min": 1300,
"typ": null,
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"source_page": 5,
"source": "datasheet"
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{
"name": "Clock HIGH time",
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"source_page": 5,
"source": "datasheet"
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{
"name": "Input data setup time",
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"min": 100,
"typ": null,
"max": null,
"conditions": "From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD.",
"source_page": 5,
"source": "datasheet"
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{
"name": "Input data hold time",
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"name": "STOP condition setup time",
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"source_page": 5,
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"source": "datasheet"
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"source_page": 4,
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