ISL1208IB8Z from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	X1	input	Input of an inverting amplifier intended for one pin of an external 32.768kHz quartz crystal; X1 can also be driven directly from a 32.768kHz source.
2	X2	output	Output of an inverting amplifier intended for connection to the other pin of an external 32.768kHz quartz crystal.
3	VBAT	power_in	Backup supply voltage input that powers the device if VDD fails; tie to ground if not used.
4	GND	power_in	Ground.
5	SDA	bidirectional	Serial data pin transferring data into and out of the device; open-drain output that may be wire-OR'ed with other open-drain or open-collector outputs and requires a pull-up resistor.
6	SCL	input	Serial clock input used to clock all serial data into and out of the device.
7	IRQ/FOUT	output	Multi-function open-drain active-low pin used as interrupt output or frequency output, with the function set via the configuration register.
8	VDD	power_in	Main power supply pin.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Clock And Timing
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Main power supply voltage	VDD	2.7		5.5	V		4
Battery supply voltage	VBAT	1.8		5.5	V		4
Operating temperature range (RTC)		-40		85	°C	RTC Temperature	4
Voltage on VDD, VBAT, SCL, SDA, IRQ pins		-0.5		7	V	respect to GND	4
Voltage on X1 and X2 pins, VDD mode		-0.5			V	respect to GND; VDD mode upper limit printed as VDD + 0.5	4
Voltage on X1 and X2 pins, VBAT mode		-0.5			V	respect to GND; VBAT mode upper limit printed as VBAT + 0.5	4
Storage temperature		-65		150	°C		4
Supply current (IDD1)	IDD1		2	6	µA	VDD = 5V	4
Supply current (IDD1)	IDD1		1.2	4	µA	VDD = 3V	4
Supply current with I2C active (IDD2)	IDD2		40	120	µA	VDD = 5V	4
Supply current, low power mode (IDD3)	IDD3		1.4	5	µA	VDD = 5V, LPMODE = 1	4
Battery supply current	IBAT		400	950	nA	VBAT = 3V	4
Input leakage current on SCL	ILI			100	nA		4
I/O leakage current on SDA	ILO			100	nA		4
VBAT mode threshold	VTRIP	1.6	2.2	2.6	V		4
VTRIP hysteresis	VTRIPHYS	10	30	75	mV		4
VBAT hysteresis	VBATHYS	15	50	100	mV		4
IRQ/FOUT output low voltage	VOL			0.4	V	VDD = 5V, IOL = 3mA	4
VDD negative slew rate	VDD SR-	10			V/ms		4
SDA and SCL input buffer LOW voltage	VIL	-0.3			V		5
SDA output buffer LOW voltage	VOL	0		0.4	V	Sinking 3mA	5
SCL frequency	fSCL			400	kHz		5
Pulse width suppression time at SDA and SCL inputs	tIN			50	ns	Any pulse narrower than the max spec is suppressed.	5
SCL falling edge to SDA output data valid	tAA			900	ns	SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window.	5
Bus free time before new transmission	tBUF	1300			ns	SDA crossing 70% of VDD during STOP, to SDA crossing 70% of VDD during following START.	5
Clock LOW time	tLOW	1300			ns	Measured at the 30% of VDD crossing.	5
Clock HIGH time	tHIGH	600			ns	Measured at the 70% of VDD crossing.	5
START condition setup time	tSU:STA	600			ns	SCL rising edge to SDA falling edge. Both crossing 70% of VDD.	5
START condition hold time	tHD:STA	600			ns	From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD.	5
Input data setup time	tSU:DAT	100			ns	From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD.	5
Input data hold time	tHD:DAT	20		900	ns	From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window.	5
STOP condition setup time	tSU:STO	600			ns	From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD.	5
STOP condition hold time	tHD:STO	600			ns	From SDA rising edge to SCL falling edge. Both crossing 70% of VDD.	5
Output data hold time	tDH	0			ns	From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window.	5
SDA and SCL rise time	tR			300	ns	From 30% to 70% of VDD	5
SDA and SCL fall time	tF			300	ns	From 70% to 30% of VDD	5
Capacitive loading of SDA or SCL	Cb	10		400	pF	Total on-chip and off-chip	5
SDA and SCL bus pull-up resistor (off-chip)	Rpu	1			kΩ	Off-chip	6
Junction-to-ambient thermal resistance, SOIC	θJA		108		°C/W	Free air, high-effective thermal conductivity test board (Note 5)	4
Junction-to-case thermal resistance, SOIC	θJC		55		°C/W	Case temperature at package top center (Note 7)	4

CAD (KiCad official)

Symbol: ISL1208IB8Z
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: isl1208ib8z-etched.step / isl1208ib8z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl1208ib8z.step / isl1208ib8z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (25 pp, sha256 859361ad9f8cf201, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ISL1208IB8Z

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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