IS25LP080D-JNLE-TR

{
  "slug": "is25lp080d-jnle-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "memory",
    "is25lp080d-jnle-tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "is25lp080d-jnle-tr.kicad_sym",
    "is25lp080d-jnle-tr.kicad_mod",
    "is25lp080d-jnle-tr.glb",
    "is25lp080d-jnle-tr.step",
    "is25lp080d-jnle-tr.lbr",
    "docs/hero.png",
    "docs/is25lp080d-jnle-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "is25lp080d-jnle-tr-hero.glb",
    "is25lp080d-jnle-tr-hero.overlay.json",
    "is25lp080d-jnle-tr-etched.glb"
  ],
  "component": {
    "mpn": "IS25LP080D-JNLE-TR",
    "manufacturer": "ISSI Integrated Silicon Solution",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "NOR FLASH",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589785497573748736",
    "parts": {
      "symbol": "is25lp080d-jnle-tr.kicad_sym",
      "footprint": "is25lp080d-jnle-tr.kicad_mod",
      "model_3d": "is25lp080d-jnle-tr-hero.glb",
      "model_3d_plain": "is25lp080d-jnle-tr-etched.glb",
      "model_3d_step": "is25lp080d-jnle-tr-etched.step",
      "model_3d_step_plain": "is25lp080d-jnle-tr.step",
      "lbr": "is25lp080d-jnle-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C521286"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T21:43:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CE#",
        "type": "input",
        "description": "Chip Enable: driving CE# high deselects the device and puts outputs in high impedance, while pulling it low selects the device; after power-up CE# must go from high to low before a new instruction is accepted."
      },
      {
        "number": "2",
        "name": "SO (IO1)",
        "type": "bidirectional",
        "description": "Serial Data Output in standard SPI, read on the falling edge of SCK; becomes bidirectional IO1 in Dual and Quad SPI mode (and QPI mode)."
      },
      {
        "number": "3",
        "name": "WP# (IO2)",
        "type": "bidirectional",
        "description": "Write Protect: with SRWD set to 1 and WP# pulled low, the Status Register bits (SRWD, QE, BP3-BP0) are write-protected; when QE=1 this pin is used as IO2 and the WP# function is not available."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground: connect to ground when referenced to Vcc."
      },
      {
        "number": "5",
        "name": "SI (IO0)",
        "type": "bidirectional",
        "description": "Serial Data Input in standard SPI, sampled on the rising edge of SCK; becomes bidirectional IO0 in Dual and Quad SPI mode (and QPI mode)."
      },
      {
        "number": "6",
        "name": "SCK",
        "type": "input",
        "description": "Serial Data Clock: synchronized clock for input and output timing operations."
      },
      {
        "number": "7",
        "name": "HOLD# or RESET# (IO3)",
        "type": "bidirectional",
        "description": "When QE=0, HOLD# (active low, default when P7=0) pauses serial communication with SO at high impedance, or RESET# (hardware reset, selected when P7=1) returns the memory to reset mode with output High-Z; when QE=1 this pin is IO3."
      },
      {
        "number": "8",
        "name": "Vcc",
        "type": "power_in",
        "description": "Power: device core power supply (IS25LP 2.30V to 3.60V; IS25WP 1.65V to 1.95V per the features list)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The 8-pin SOIC 150mil (N) is the package encoded in the MPN (IS25LP080D-JNLE: J=standard option, N=8; The page 7 diagram also shows a second, differently ordered label set for the same package family. I; The suffix '-TR' (tape and reel) in the MPN does not appear in the ordering information on page 112;"
        ],
        "pages_sent": 10,
        "cost_usd": 0.0549,
        "at": "2026-10-18T21:42:59"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589785497573748736",
        "pages": 113,
        "sha256": "ef06a5ada10e0487",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "is25lp080d-jnle-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "is25lp080d-jnle-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2f797706afd954d3fae1c815f43af7e201c09054259c9b1e1f5dc221b52456b2",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}