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IS25LP080D-JNLE-TR

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ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IS25LP080D-JNLE-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8

IS25LP080D-JNLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: driving CE# high deselects the device and puts outputs in high impedance, while pulling it low selects the device; after power-up CE# must go from high to low before a new instruction is accepted.
2 SO (IO1) bidirectional Serial Data Output in standard SPI, read on the falling edge of SCK; becomes bidirectional IO1 in Dual and Quad SPI mode (and QPI mode).
3 WP# (IO2) bidirectional Write Protect: with SRWD set to 1 and WP# pulled low, the Status Register bits (SRWD, QE, BP3-BP0) are write-protected; when QE=1 this pin is used as IO2 and the WP# function is not available.
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional Serial Data Input in standard SPI, sampled on the rising edge of SCK; becomes bidirectional IO0 in Dual and Quad SPI mode (and QPI mode).
6 SCK input Serial Data Clock: synchronized clock for input and output timing operations.
7 HOLD# or RESET# (IO3) bidirectional When QE=0, HOLD# (active low, default when P7=0) pauses serial communication with SO at high impedance, or RESET# (hardware reset, selected when P7=1) returns the memory to reset mode with output High-Z; when QE=1 this pin is IO3.
8 Vcc power_in Power: device core power supply (IS25LP 2.30V to 3.60V; IS25WP 1.65V to 1.95V per the features list).

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 96
Input Voltage with Respect to Ground on All Pins (lower limit) -0.5 V 96
All Output Voltage with Respect to Ground (lower limit) -0.5 V 96
VCC Supply Voltage (IS25LP) VCC -0.5 6 V IS25LP 96
Electrostatic Discharge Voltage (Human Body Model) -2000 2000 V Human Body Model 96
Operating Temperature, Extended Grade E -40 105 °C Extended Grade E 96
VCC Power Supply (IS25LP) VCC 2.3 3 3.6 V IS25LP 96
VCC Active Read current ICC1 4 12 mA NORD at 50MHz 97
VCC Active Read current ICC1 6 14 mA FRD Single at 133MHz 97
VCC Active Read current ICC1 8 15 mA FRD Dual at 133MHz 97
VCC Active Read current ICC1 10 17 mA FRD Quad at 133MHz 97
VCC Active Read current ICC1 9 16 mA FRD Quad at 104MHz 97
VCC Program Current ICC2 25 mA CE# = VCC, 105°C 97
VCC WRSR Current ICC3 25 mA CE# = VCC, 105°C 97
VCC Erase Current (SER/BER32/BER64) ICC4 25 mA CE# = VCC, 105°C 97
VCC Erase Current (CE) ICC5 25 mA CE# = VCC, 105°C 97
VCC Standby Current CMOS ISB1 20 µA CE# = VCC, VIN = GND or VCC, 105°C 97
Deep power down current (IS25LP) ISB2 15 µA CE# = VCC, VIN = GND or VCC, 105°C 97
Input Leakage Current ILI -1 1 µA VIN = 0V to VCC 97
Output Leakage Current ILO -1 1 µA VIN = 0V to VCC 97
Input Low Voltage (lower limit) VIL -0.5 V 97
Output Low Voltage VOL 0.2 V IOL = 100 µA 97
Input Capacitance (CE#, SCK) CIN 6 pF VIN = 0V 98
Input/Output Capacitance (other pins) CIN/OUT 8 pF VIN/OUT = 0V 98
Clock Frequency for fast read (SPI, Dual, Dual I/O, Quad I/O, QPI) fCT 0 133 MHz 99
Clock Frequency for fast read DTR (SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, QPI DTR) fCT 0 66 MHz 99
Clock Frequency for read (03h) fC 0 50 MHz 99
CE# High Time tCEH 7 ns 99
CE# Setup Time tCS 5 ns 99
CE# Hold Time tCH 5 ns 99
CE# Not Active Setup Time tSHCH 2.7 ns 99
CE# Not Active Hold Time tCHSL 2.7 ns 99
Data In Setup Time (STR) tDS 2 ns STR 99
Data In Setup Time (DTR) tDS 1.5 ns DTR 99
Data in Hold Time (STR) tDH 2 ns STR 99
Data in Hold Time (DTR) tDH 1.5 ns DTR 99
Output Valid tV 7 ns @ 133MHz (CL = 15pF) 99
Output Valid tV 8 ns @ 104MHz (CL = 30pF) 99
Output Hold Time tOH 2 ns 99
Output Disable Time tDIS 8 ns 99
HOLD Active Setup Time relative to SCK tHLCH 2 ns 99
HOLD Active Hold Time relative to SCK tCHHH 2 ns 99
HOLD Not Active Setup Time relative to SCK tHHCH 2 ns 99
HOLD Not Active Hold Time relative to SCK tCHHL 2 ns 99
Sector Erase Time (4Kbyte) tEC 70 300 ms 99
Block Erase Time (32Kbyte) tEC 0.1 0.5 s 99
Block Erase Time (64Kbyte) tEC 0.15 1 s 99
Chip Erase Time (8Mb) tEC 2 6 s 8Mb 99
Page Program Time tPP 0.2 0.8 ms 99
Write Status Register time tW 2 15 ms 100
Suspend to read ready tSUS 100 µs 100
Resume to next suspend TRS 80 µs 100
Vcc(min) to CE# Low tVCE 300 us 104
Byte Program 8 40 µs 105
Endurance 100000 cycles JEDEC Standard A117 105
Data Retention 20 years JEDEC Standard A117 105
Latch-Up -100 100 mA JEDEC Standard 78 105

CAD (KiCad official)

  • Symbol: IS25LP080D-JNLE-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: is25lp080d-jnle-tr-etched.step / is25lp080d-jnle-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp080d-jnle-tr.step / is25lp080d-jnle-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (113 pp, sha256 ef06a5ada10e0487, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF