IS25LP020E-JNLE-TR

{
  "slug": "is25lp020e-jnle-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "memory",
    "is25lp020e-jnle-tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "is25lp020e-jnle-tr.kicad_sym",
    "is25lp020e-jnle-tr.kicad_mod",
    "is25lp020e-jnle-tr.glb",
    "is25lp020e-jnle-tr.step",
    "is25lp020e-jnle-tr.lbr",
    "docs/hero.png",
    "docs/is25lp020e-jnle-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "is25lp020e-jnle-tr-hero.glb",
    "is25lp020e-jnle-tr-hero.overlay.json",
    "is25lp020e-jnle-tr-etched.glb"
  ],
  "component": {
    "mpn": "IS25LP020E-JNLE-TR",
    "manufacturer": "ISSI Integrated Silicon Solution",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "NOR FLASH",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600666731489091584",
    "parts": {
      "symbol": "is25lp020e-jnle-tr.kicad_sym",
      "footprint": "is25lp020e-jnle-tr.kicad_mod",
      "model_3d": "is25lp020e-jnle-tr-hero.glb",
      "model_3d_plain": "is25lp020e-jnle-tr-etched.glb",
      "model_3d_step": "is25lp020e-jnle-tr-etched.step",
      "model_3d_step_plain": "is25lp020e-jnle-tr.step",
      "lbr": "is25lp020e-jnle-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C7211260",
      "digikey": "706-IS25LP020E-JNLE-TR-ND",
      "mouser": "870-25LP020JNLTR"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T20:36:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "706-IS25LP020E-JNLE-TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "870-25LP020JNLTR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CE#",
        "type": "input",
        "description": "Chip Enable: driving CE# high deselects the device and puts the outputs in high impedance, while CE# must go high-to-low before the first instruction is accepted after power-up."
      },
      {
        "number": "2",
        "name": "SO (IO1)",
        "type": "bidirectional",
        "description": "Serial Data Output in standard SPI (read on the falling edge of SCK), and bidirectional IO1 in Dual and Quad SPI modes and in QPI mode."
      },
      {
        "number": "3",
        "name": "WP# (IO2)",
        "type": "bidirectional",
        "description": "Write Protect pin that protects the Status Register together with the SRWD bit when pulled low, and becomes IO2 for Quad operation (WP# function unavailable when QE = 1)."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground: connect to ground when referenced to Vcc."
      },
      {
        "number": "5",
        "name": "SI (IO0)",
        "type": "bidirectional",
        "description": "Serial Data Input in standard SPI (data latched on the rising edge of SCK), and bidirectional IO0 in Dual, Quad and QPI modes."
      },
      {
        "number": "6",
        "name": "SCK",
        "type": "input",
        "description": "Serial Data Clock: synchronizes input and output timing operations."
      },
      {
        "number": "7",
        "name": "HOLD# (IO3)",
        "type": "bidirectional",
        "description": "Hold pin that pauses serial communication while CE# is low (active low, SO goes high impedance), and becomes IO3 when QE = 1 (HOLD# function unavailable)."
      },
      {
        "number": "8",
        "name": "Vcc",
        "type": "power_in",
        "description": "Power: device core power supply; IS25LP range is 2.30V to 3.60V per the datasheet."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The page 6 pin diagram is garbled in the text extraction, so pin numbers were mapped from the standa; The MPN suffix -JNLE decodes per the page 92 ordering key to Option J, Package N (8-pin SOIC 150mil)"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0521,
        "at": "2026-10-20T20:33:42"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600666731489091584",
        "pages": 93,
        "sha256": "682d1cb75600d9cd",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "is25lp020e-jnle-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "is25lp020e-jnle-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "95af6dd79dcd7097e2ec7c762dc68563be48aafc96111e92e10c819689cd47e6",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}