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IS25LP020E-JNLE-TR

Public Made by Adom

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ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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IS25LP020E-JNLE-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8

IS25LP020E-JNLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: driving CE# high deselects the device and puts the outputs in high impedance, while CE# must go high-to-low before the first instruction is accepted after power-up.
2 SO (IO1) bidirectional Serial Data Output in standard SPI (read on the falling edge of SCK), and bidirectional IO1 in Dual and Quad SPI modes and in QPI mode.
3 WP# (IO2) bidirectional Write Protect pin that protects the Status Register together with the SRWD bit when pulled low, and becomes IO2 for Quad operation (WP# function unavailable when QE = 1).
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional Serial Data Input in standard SPI (data latched on the rising edge of SCK), and bidirectional IO0 in Dual, Quad and QPI modes.
6 SCK input Serial Data Clock: synchronizes input and output timing operations.
7 HOLD# (IO3) bidirectional Hold pin that pauses serial communication while CE# is low (active low, SO goes high impedance), and becomes IO3 when QE = 1 (HOLD# function unavailable).
8 Vcc power_in Power: device core power supply; IS25LP range is 2.30V to 3.60V per the datasheet.

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 77
Surface Mount Lead Soldering Temperature (Lead-free Package) 260 °C Lead-free package, 3 seconds 77
VCC Supply Voltage (IS25LP) VCC -0.5 6 V IS25LP 77
Input Voltage with Respect to Ground on All Pins (max printed as VCC + 0.5V) -0.5 V 77
All Output Voltage with Respect to Ground (max printed as VCC + 0.5V) -0.5 V 77
Ambient Operating Temperature, Extended Grade E -40 105 °C Extended Grade E 77
VCC Power Supply (IS25LP) VCC 2.3 3 3.6 V IS25LP; 3.0V Typ 77
VCC Active Read current NORD ICC1 6 8 mA NORD at 50MHz 78
VCC Active Read current FRD Single ICC1 7 9 mA FRD Single at 104MHz 78
VCC Active Read current FRD Dual ICC1 8 10 mA FRD Dual at 104MHz 78
VCC Active Read current FRD Quad ICC1 10 12 mA FRD Quad at 104MHz 78
VCC Program Current 85°C ICC2 15 20 mA CE# = VCC, 85°C 78
VCC Program Current 105°C ICC2 20 mA CE# = VCC, 105°C 78
VCC Program Current 125°C ICC2 20 mA CE# = VCC, 125°C 78
VCC WRSR Current 85°C ICC3 15 20 mA CE# = VCC, 85°C 78
VCC WRSR Current 105°C ICC3 20 mA CE# = VCC, 105°C 78
VCC WRSR Current 125°C ICC3 20 mA CE# = VCC, 125°C 78
VCC Erase Current (SER/BER4K/BER64K) 85°C ICC4 15 20 mA CE# = VCC, 85°C 78
VCC Erase Current (SER/BER4K/BER64K) 105°C ICC4 20 mA CE# = VCC, 105°C 78
VCC Erase Current (SER/BER4K/BER64K) 125°C ICC4 20 mA CE# = VCC, 125°C 78
VCC Standby Current CMOS 85°C ISB1 17 35 µA CE# = VCC, VIN = GND or VCC, 85°C 78
VCC Standby Current CMOS 105°C ISB1 40 µA CE# = VCC, VIN = GND or VCC, 105°C 78
VCC Standby Current CMOS 125°C ISB1 45 µA CE# = VCC, VIN = GND or VCC, 125°C 78
Deep Power Down Current (IS25LP) 85°C ISB2 6 15 µA IS25LP; CE# = VCC, VIN = GND or VCC, 85°C 78
Deep Power Down Current (IS25LP) 105°C ISB2 18 µA IS25LP; CE# = VCC, VIN = GND or VCC, 105°C 78
Deep Power Down Current (IS25LP) 125°C ISB2 20 µA IS25LP; CE# = VCC, VIN = GND or VCC, 125°C 78
Input Leakage Current ILI 1 VIN = 0V to VCC 78
Output Leakage Current ILO 1 VIN = 0V to VCC 78
Input Low Voltage (max printed as 0.3VCC) VIL -0.5 V 78
Output Low Voltage VOL 0.2 V VMIN < VCC < VMAX, IOL = 100 µA 78
Load Capacitance CL 30 pF 79
Input Rise and Fall Times TR,TF 5 ns 79
Input Capacitance (CE#, SCK) CIN 6 pF VIN = 0V; TA = 25°C, VCC=3V for IS25LP, 1MHz 79
Input/Output Capacitance (other pins) CIN/OUT 8 pF VIN/OUT = 0V; TA = 25°C, VCC=3V for IS25LP, 1MHz 79
Clock Frequency for fast read mode fCT 0 104 MHz 80
Clock Frequency for read mode fC 0 50 MHz 80
SCK High Time tCKH 4 ns 80
SCK Low Time tCKL 4 ns 80
CE# High Time tCEH 7 ns 80
CE# Setup Time tCS 5 ns 80
CE# Hold Time tCH 5 ns 80
CE# Not Active Hold Time tCHSL 5 ns 80
CE# Not Active Setup Time tSHCH 5 ns 80
Data In Setup Time tDS 2 ns 80
Data In Hold Time tDH 2 ns 80
Output Valid tV 8 ns 80
Output Hold Time tOH 2 ns 80
Output Disable Time tDIS 8 ns 80
Write Protect Setup Time tWHSL 20 ns Only applicable when SRWD is set at 1 80
Write Protect Hold Time tSHWL 100 ns Only applicable when SRWD is set at 1 80
HOLD to Output Low Z tLZ 12 ns 80
HOLD to Output High Z tHZ 12 ns 80
Sector Erase Time (4Kbyte) tEC 70 300 ms 80
Block Erase Time (32Kbyte) 130 500 ms 80
Block Erase Time (64Kbyte) 200 1000 ms Not applicable to 256Kb and 512Kb (footnote 4) 80
Chip Erase Time 2Mb 0.75 2 s 80
Page Program Time tPP 0.45 1.2 ms 80
VCC Erase Current (CE) 85°C ICC5 15 20 mA CE# = VCC, 85°C 78
VCC Erase Current (CE) 105°C ICC5 20 mA CE# = VCC, 105°C 78
VCC Erase Current (CE) 125°C ICC5 20 mA CE# = VCC, 125°C 78

CAD (KiCad official)

  • Symbol: IS25LP020E-JNLE-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: is25lp020e-jnle-tr-etched.step / is25lp020e-jnle-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp020e-jnle-tr.step / is25lp020e-jnle-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (93 pp, sha256 682d1cb75600d9cd, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF