component

IS25LP020E-JNLA3-TR

Public Made by Adom

by adom

ISSI Integrated Silicon Solution NOR FLASH, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryis25lp020e-jnla3-trfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers is25lp020e-jnla3-tr: viewers · Ray 1d ago
is25lp020e-jnla3-tr-etched.glb Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr-etched.step is25lp020e-jnla3-tr: factory component page (tier=lcsc) · Ray 1d ago
is25lp020e-jnla3-tr-hero.glb is25lp020e-jnla3-tr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
is25lp020e-jnla3-tr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr.glb Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr.kicad_mod Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr.kicad_sym Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr.lbr Publish 0.1.0 · Ray 1d ago
is25lp020e-jnla3-tr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago

IS25LP020E-JNLA3-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOP-8

IS25LP020E-JNLA3-TR from ISSI Integrated Silicon Solution, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: when high the device is deselected and outputs are high impedance, and after power-up CE# must transition from high to low before a new instruction is accepted.
2 SO (IO1) bidirectional Serial Data Output for standard SPI, read on the falling edge of SCK; in Dual and Quad SPI mode it becomes the bidirectional IO1 pin.
3 WP# (IO2) bidirectional Write Protect (active low) protects the Status Register together with the SRWD bit, and when QE is set to 1 it is used as IO2 so the write-protect function is not available.
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional Serial Data Input for instructions, addresses, or data, sampled on the rising edge of SCK; in Dual and Quad SPI mode it becomes the bidirectional IO0 pin.
6 SCK input Serial Data Clock: synchronizes the input and output timing operations.
7 HOLD# (IO3) bidirectional Hold (active low) pauses serial communication without resetting the serial sequence while CE# is low; when QE is set to 1 it becomes IO3 and the HOLD# function is not available.
8 Vcc power_in Device core power supply; the IS25LP part is specified for 2.30V to 3.60V single voltage supply.

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 77
Surface Mount Lead Soldering Temperature 260 °C Lead-free package, 3 seconds 77
Input Voltage with Respect to Ground on All Pins -0.5 V Lower limit; upper limit printed as VCC + 0.5V 77
All Output Voltage with Respect to Ground -0.5 V Lower limit; upper limit printed as VCC + 0.5V 77
VCC Supply Voltage VCC -0.5 6 V IS25LP 77
Ambient Operating Temperature -40 125 °C Automotive Grade A3 77
VCC Power Supply VCC 2.3 3 3.6 V IS25LP; min VMIN, max VMAX; typ 3.0V 77
VCC Active Read current ICC1 6 8 mA NORD at 50MHz 78
VCC Active Read current ICC1 7 9 mA FRD Single at 104MHz 78
VCC Active Read current ICC1 8 10 mA FRD Dual at 104MHz 78
VCC Active Read current ICC1 10 12 mA FRD Quad at 104MHz 78
VCC Program Current ICC2 15 20 mA CE# = VCC, 85°C 78
VCC Program Current ICC2 20 mA CE# = VCC, 105°C 78
VCC WRSR Current ICC3 15 20 mA CE# = VCC, 85°C 78
VCC WRSR Current ICC3 20 mA CE# = VCC, 105°C 78
VCC Standby Current CMOS ISB1 17 35 µA CE# = VCC, VIN = GND or VCC, 85°C 78
VCC Standby Current CMOS ISB1 40 µA CE# = VCC, VIN = GND or VCC, 105°C 78
VCC Standby Current CMOS ISB1 45 µA CE# = VCC, VIN = GND or VCC, 125°C 78
Deep power down current (IS25LP) ISB2 6 15 µA IS25LP, CE# = VCC, VIN = GND or VCC, 85°C 78
Deep power down current (IS25LP) ISB2 18 µA IS25LP, CE# = VCC, VIN = GND or VCC, 105°C 78
Deep power down current (IS25LP) ISB2 20 µA IS25LP, CE# = VCC, VIN = GND or VCC, 125°C 78
Input Leakage Current ILI 1 µA VIN = 0V to VCC 78
Output Leakage Current ILO 1 µA VIN = 0V to VCC 78
Input Low Voltage VIL -0.5 V Lower limit 78
Input Low Voltage VIL 0.3 xVCC Max = 0.3VCC 78
Input High Voltage VIH 0.7 xVCC Min = 0.7VCC 78
Input High Voltage VIH 0.3 V above VCC Max = VCC + 0.3V (offset above VCC) 78
Output Low Voltage VOL 0.2 V VMIN < VCC < VMAX, IOL = 100 µA 78
Output High Voltage VOH -0.2 V below VCC IOH = -100 µA; min = VCC - 0.2V (offset below VCC) 78
Clock Frequency for fast read mode fCT 0 104 MHz 80
Clock Frequency for read mode fC 0 50 MHz 80
SCK High Time tCKH 4 ns 80
SCK Low Time tCKL 4 ns 80
CE# High Time tCEH 7 ns 80
CE# Setup Time tCS 5 ns 80
CE# Hold Time tCH 5 ns 80
CE# Not Active Hold Time tCHSL 5 ns 80
CE# Not Active Setup Time tSHCH 5 ns 80
Data In Setup Time tDS 2 ns 80
Data In Hold Time tDH 2 ns 80
Output Valid tV 8 ns 80
Output Hold Time tOH 2 ns 80
Output Disable Time tDIS 8 ns 80
Sector Erase Time (4Kbyte) tEC 70 300 ms 80
Block Erase Time (32Kbyte) 130 500 ms 80
Block Erase Time (64Kbyte) 200 1000 ms Note 4: not applicable to 256Kb and 512Kb; applies to 2Mb 80
Chip Erase Time (2Mb) 0.75 2 s 2Mb 80
Page Program Time tPP 0.45 1.2 ms 80
Byte Program 8 40 µs 85
Release deep power down (IS25LP) tres1 3 µs IS25LP 80
Deep power down tDP 3 µs 80
Write Status Register time tW 2 10 ms 80
Suspend to read ready tSUS 100 µs 80
Resume to next suspend tRS 80 µs 80
Vcc(min) to CE# Low tVCE 300 us 84
Write Inhibit Voltage (IS25LP) VWI 2.1 V IS25LP 84
Endurance 100000 cycles JEDEC Standard A117 85
Data Retention 20 years JEDEC Standard A117 85

CAD (KiCad official)

  • Symbol: IS25LP020E-JNLA3-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: is25lp020e-jnla3-tr-etched.step / is25lp020e-jnla3-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp020e-jnla3-tr.step / is25lp020e-jnla3-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (93 pp, sha256 682d1cb75600d9cd, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF