component
IRF8313TR
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IRF8313TR
UMW · MOSFETs · SOP-8
IRF8313TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of MOSFET 1 (S1); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device. |
| 2 | G1 | input | Gate terminal of MOSFET 1 (G1); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings. |
| 3 | S2 | passive | Source terminal of MOSFET 2 (S2); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device. |
| 4 | G2 | input | Gate terminal of MOSFET 2 (G2); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings. |
| 5 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 6 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 7 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 8 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
IRF8313TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
irf8313tr-etched.step/irf8313tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);irf8313tr.step/irf8313tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (9 pp, sha256
64b82ebbb4ddfb23, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IRF8313TR
**UMW** · MOSFETs · SOP-8
IRF8313TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of MOSFET 1 (S1); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device. |
| 2 | G1 | input | Gate terminal of MOSFET 1 (G1); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings. |
| 3 | S2 | passive | Source terminal of MOSFET 2 (S2); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device. |
| 4 | G2 | input | Gate terminal of MOSFET 2 (G2); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings. |
| 5 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 6 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 7 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
| 8 | D1,D2 | passive | Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `IRF8313TR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `irf8313tr-etched.step` / `irf8313tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irf8313tr.step` / `irf8313tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755879585898872832) (9 pp, sha256 `64b82ebbb4ddfb23`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/irf8313tr-datasheet.pdf)