component

IRF8313TR

Public Made by Adom

by adom

UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsirf8313trfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4h ago
viewers irf8313tr: viewers · Ray 4h ago
irf8313tr-etched.glb irf8313tr: factory component page (tier=lcsc) · Ray 4h ago
irf8313tr-etched.step irf8313tr: factory component page (tier=lcsc) · Ray 4h ago
irf8313tr-hero.glb irf8313tr: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
irf8313tr-hero.overlay.json Publish 0.1.0 · Ray 4h ago
irf8313tr.glb Publish 0.1.0 · Ray 4h ago
irf8313tr.kicad_mod Publish 0.1.0 · Ray 4h ago
irf8313tr.kicad_sym Publish 0.1.0 · Ray 4h ago
irf8313tr.lbr Publish 0.1.0 · Ray 4h ago
irf8313tr.step Publish 0.1.0 · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago

IRF8313TR

UMW · MOSFETs · SOP-8

IRF8313TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of MOSFET 1 (S1); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device.
2 G1 input Gate terminal of MOSFET 1 (G1); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings.
3 S2 passive Source terminal of MOSFET 2 (S2); the datasheet gives no separate electrical limit for this pin beyond the absolute maximum ratings for the device.
4 G2 input Gate terminal of MOSFET 2 (G2); the datasheet gives VGS(th) of 1 V to 2.5 V for the device and ±20 V maximum gate-source voltage in the absolute maximum ratings.
5 D1,D2 passive Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device.
6 D1,D2 passive Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device.
7 D1,D2 passive Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device.
8 D1,D2 passive Drain terminal shared by the two MOSFET drains (D1/D2); the datasheet gives VDS maximum of 30 V for the device.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: IRF8313TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: irf8313tr-etched.step / irf8313tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irf8313tr.step / irf8313tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (9 pp, sha256 64b82ebbb4ddfb23, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF