component
IRF8113TR
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IRF8113TR
UMW · MOSFETs · SOP-8
IRF8113TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 2 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 3 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 4 | G | passive | GATE pin of the MOSFET; gate-to-source voltage is rated at ±20 V (absolute maximum, TA=25°C). |
| 5 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 6-8. |
| 6 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5, 7 and 8. |
| 7 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5, 6 and 8. |
| 8 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5-7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 30 | V | ID=250µA, VGS=0V | 3 | ||
| Gate Threshold Voltage | VGS(th) | 1.5 | 2.2 | V | VDS=VGS, ID=250μA | 3 | |
| Gate-to-Source Forward Leakage | IGSS | 100 | nA | VGS=20V | 3 | ||
| Gate-to-Source Reverse Leakage | IGSS | -100 | nA | VGS=-20V | 3 | ||
| Drain-to-Source Leakage Current | IDSS | 1 | µA | VDS=24V, VGS=0V | 3 | ||
| Drain-to-Source Leakage Current | IDSS | 150 | µA | VDS=24V, VGS=0V, TJ=125°C | 3 | ||
| Static Drain-to-Source On-Resistance | RDS(ON) | 4.7 | 5.6 | mΩ | VGS=10V, ID=17.2A | 3 | |
| Static Drain-to-Source On-Resistance | RDS(ON) | 5.8 | 6.8 | mΩ | VGS=4.5V, ID=13.8A | 3 | |
| Drain-Source Voltage | VDS | 30 | V | 1 | |||
| Gate-to-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current, VGS=10V | ID | 17.2 | A | TA=25°C | 1 | ||
| Continuous Drain Current, VGS=10V | ID | 13.8 | A | TA=70°C | 1 | ||
| Pulsed Drain Current | IDM | 135 | A | 1 | |||
| Power Dissipation | PD | 2.5 | W | TA=25°C | 1 | ||
| Power Dissipation | PD | 1.6 | W | TA=70°C | 1 | ||
| Linear Derating Factor | 0.02 | W/°C | 1 | ||||
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 1 | ||
| Junction-to-Drain Lead | RθJL | 20 | °C/W | 2 | |||
| Junction-to-Ambient | RθJA | 50 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
IRF8113TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
irf8113tr-etched.step/irf8113tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);irf8113tr.step/irf8113tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (12 pp, sha256
061f2f1e2ef37358, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IRF8113TR
**UMW** · MOSFETs · SOP-8
IRF8113TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 2 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 3 | S | passive | SOURCE pin of the N-channel MOSFET; the datasheet gives no separate pin limit for it beyond the 30 V VDS and ±20 V VGS absolute maximum ratings. |
| 4 | G | passive | GATE pin of the MOSFET; gate-to-source voltage is rated at ±20 V (absolute maximum, TA=25°C). |
| 5 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 6-8. |
| 6 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5, 7 and 8. |
| 7 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5, 6 and 8. |
| 8 | D | passive | DRAIN pin of the MOSFET; drain-to-source voltage is rated at 30 V (absolute maximum), and the drain is internally common with pins 5-7. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 30 | | | V | ID=250µA, VGS=0V | 3 |
| Gate Threshold Voltage | VGS(th) | 1.5 | | 2.2 | V | VDS=VGS, ID=250μA | 3 |
| Gate-to-Source Forward Leakage | IGSS | | | 100 | nA | VGS=20V | 3 |
| Gate-to-Source Reverse Leakage | IGSS | -100 | | | nA | VGS=-20V | 3 |
| Drain-to-Source Leakage Current | IDSS | | | 1 | µA | VDS=24V, VGS=0V | 3 |
| Drain-to-Source Leakage Current | IDSS | | | 150 | µA | VDS=24V, VGS=0V, TJ=125°C | 3 |
| Static Drain-to-Source On-Resistance | RDS(ON) | | 4.7 | 5.6 | mΩ | VGS=10V, ID=17.2A | 3 |
| Static Drain-to-Source On-Resistance | RDS(ON) | | 5.8 | 6.8 | mΩ | VGS=4.5V, ID=13.8A | 3 |
| Drain-Source Voltage | VDS | | | 30 | V | | 1 |
| Gate-to-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous Drain Current, VGS=10V | ID | | | 17.2 | A | TA=25°C | 1 |
| Continuous Drain Current, VGS=10V | ID | | | 13.8 | A | TA=70°C | 1 |
| Pulsed Drain Current | IDM | | | 135 | A | | 1 |
| Power Dissipation | PD | | | 2.5 | W | TA=25°C | 1 |
| Power Dissipation | PD | | | 1.6 | W | TA=70°C | 1 |
| Linear Derating Factor | | | | 0.02 | W/°C | | 1 |
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 1 |
| Junction-to-Drain Lead | RθJL | | 20 | | °C/W | | 2 |
| Junction-to-Ambient | RθJA | | | 50 | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `IRF8113TR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `irf8113tr-etched.step` / `irf8113tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irf8113tr.step` / `irf8113tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755878222435635200) (12 pp, sha256 `061f2f1e2ef37358`, retrieved 2026-10-14, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/irf8113tr-datasheet.pdf)