component
IRF7307TR
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"type": "component",
"slug": "irf7307tr",
"title": "IRF7307TR",
"brief": "UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
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"component": {
"mpn": "IRF7307TR",
"manufacturer": "UMW",
"package": "SOP-8",
"pin_count": 8,
"category": "Transistors/Thyristors",
"subcategory": "MOSFETs",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755879314921398272",
"parts": {
"symbol": "irf7307tr.kicad_sym",
"footprint": "irf7307tr.kicad_mod",
"model_3d": "irf7307tr-hero.glb",
"model_3d_plain": "irf7307tr.glb",
"model_3d_step": "irf7307tr-etched.step",
"model_3d_step_plain": "irf7307tr.step",
"lbr": "irf7307tr.lbr"
},
"distributor_links": {
"lcsc": "C5346816"
},
"distributor_check": {
"checked_at": "2026-10-09T19:10:15Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "S1",
"type": "passive",
"description": "Source terminal of the channel-1 MOSFET; the datasheet gives no pin-level limit, so the device ratings apply (VGS ±12 V, continuous drain current 5.7 A N-ch / -4.7 A P-ch at TA=25°C)."
},
{
"number": "2",
"name": "G1",
"type": "input",
"description": "Gate terminal of the channel-1 MOSFET; gate-to-source voltage is rated ±12 V absolute maximum."
},
{
"number": "3",
"name": "S2",
"type": "passive",
"description": "Source terminal of the channel-2 MOSFET; the datasheet gives no pin-level limit, so the device ratings apply (VGS ±12 V, continuous drain current 5.7 A N-ch / -4.7 A P-ch at TA=25°C)."
},
{
"number": "4",
"name": "G2",
"type": "input",
"description": "Gate terminal of the channel-2 MOSFET; gate-to-source voltage is rated ±12 V absolute maximum."
},
{
"number": "5",
"name": "D2",
"type": "passive",
"description": "Drain terminal of the channel-2 MOSFET; drain is rated for the device's continuous and pulsed drain current limits (e.g., 21 A pulsed N-ch, -17 A pulsed P-ch at TA=25°C)."
},
{
"number": "6",
"name": "D2",
"type": "passive",
"description": "Drain terminal of the channel-2 MOSFET; drain is rated for the device's continuous and pulsed drain current limits (e.g., 21 A pulsed N-ch, -17 A pulsed P-ch at TA=25°C)."
},
{
"number": "7",
"name": "D1",
"type": "passive",
"description": "Drain terminal of the channel-1 MOSFET; drain is rated for the device's continuous and pulsed drain current limits (e.g., 21 A pulsed N-ch, -17 A pulsed P-ch at TA=25°C)."
},
{
"number": "8",
"name": "D1",
"type": "passive",
"description": "Drain terminal of the channel-1 MOSFET; drain is rated for the device's continuous and pulsed drain current limits (e.g., 21 A pulsed N-ch, -17 A pulsed P-ch at TA=25°C)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin-to-name mapping is inferred from the pinning table (groups 1,3 = SOURCE; 2,4 = GATE; 5-8 = DRAIN; Drain assignment for pins 5-8 (D2 at 5,6; D1 at 7,8) is inferred from the garbled diagram text and w; The datasheet does not explicitly state which channel (N or P) each drain/source/gate pair belongs t"
],
"pages_sent": 14,
"cost_usd": 0.0619,
"at": "2026-10-09T19:07:18"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755879314921398272",
"pages": 14,
"sha256": "c8bbb7e2ee90e3b6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
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1.75
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"zmin_mm": 0,
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"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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{
"file": "irf7307tr-etched.step",
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"sha256": "f251e66d29364a0e4d3d0891f312fd8661fab9336fea46f9d01be54d4e7d7a0a",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "UMW",
"Package": "SOP-8",
"Category": "Transistors/Thyristors",
"Pins": "8"
}
},
"variants": [],
"sections": [
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"discovery_triggers": [
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"discovery_pitch": "IRF7307TR (UMW) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
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