IR11688STRPBF

{
  "slug": "ir11688strpbf",
  "version": "0.1.0",
  "type": "component",
  "description": "Infineon Technologies Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management ics",
    "ir11688strpbf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
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    "ir11688strpbf.kicad_mod",
    "ir11688strpbf.glb",
    "ir11688strpbf.step",
    "ir11688strpbf.lbr",
    "docs/hero.png",
    "docs/ir11688strpbf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ir11688strpbf-hero.glb",
    "ir11688strpbf-hero.overlay.json",
    "ir11688strpbf-etched.glb"
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  "component": {
    "mpn": "IR11688STRPBF",
    "manufacturer": "Infineon Technologies",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management ICs",
    "subcategory": "Gate Drive ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/d08dd10aa8cbc217347c3fc09f5f8b25.pdf",
    "parts": {
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      "footprint": "ir11688strpbf.kicad_mod",
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      "model_3d_plain": "ir11688strpbf-etched.glb",
      "model_3d_step": "ir11688strpbf-etched.step",
      "model_3d_step_plain": "ir11688strpbf.step",
      "lbr": "ir11688strpbf.lbr"
    },
    "distributor_links": {
      "lcsc": "C537534"
    },
    "distributor_check": {
      "checked_at": "2026-10-22T22:58:17Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "deferred",
        "error": "shared DigiKey quota guard: 799 calls left today"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "GATE1",
        "type": "output",
        "description": "Gate drive output 1 for SR MOSFET 1 with +1A/-4A peak drive capability, gate clamped to Vcc+0.3V max."
      },
      {
        "number": "2",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage pin monitored by UVLO, operating range 4.75V to 18V (abs max 20V), needs a ceramic decoupling capacitor to GND, internally clamped around 20V."
      },
      {
        "number": "3",
        "name": "MOT",
        "type": "passive",
        "description": "Minimum on time programming pin set by an external resistor to GND (20kΩ to 150kΩ), typically programming 500ns to 2µs, max pin voltage 3.5V."
      },
      {
        "number": "4",
        "name": "VD1",
        "type": "input",
        "description": "Sync FET 1 drain voltage sense input rated -1V to 200V continuous (-3V pulse), with at most a ≤1kΩ series resistor and pF-range capacitor filter."
      },
      {
        "number": "5",
        "name": "VD2",
        "type": "input",
        "description": "Sync FET 2 drain voltage sense input rated -1V to 200V continuous (-3V pulse), with at most a ≤1kΩ series resistor and pF-range capacitor filter."
      },
      {
        "number": "6",
        "name": "VS",
        "type": "power_in",
        "description": "Sync FET source voltage sense (signal ground for the SR MOSFET sources), rated -1V to 5V, Kelvin connect to MOSFET2 source if the MOSFETs are far apart."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Analog and power ground to which internal circuit blocks and gate drivers are referenced."
      },
      {
        "number": "8",
        "name": "GATE2",
        "type": "output",
        "description": "Gate drive output 2 for SR MOSFET 2 with +1A/-4A peak drive capability, gate clamped to Vcc+0.3V max."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "2/8 pins cited to the wrong page (name found elsewhere): ['1:GATE1@p10', '8:GATE2@p10']"
        ],
        "pages_sent": 27,
        "cost_usd": 0.1137,
        "at": "2026-10-22T22:58:07"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/d08dd10aa8cbc217347c3fc09f5f8b25.pdf",
        "pages": 27,
        "sha256": "f56e8cc22a4abcd4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "centre_offset_mm": 0.0,
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        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-22",
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      },
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        "checked": "2026-10-22",
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  }
}