component

IP6525T_N

Public Made by Adom

by adom

INJOINIC IP6525T N DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ip6525t-n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ip6525t-n-etched.fit.json ip6525t-n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ip6525t-n-etched.glb ip6525t-n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ip6525t-n-etched.step ip6525t-n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ip6525t-n.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body… · Ray
ip6525t-n.kicad_mod Publish 0.1.0 · Ray
ip6525t-n.kicad_sym Publish 0.1.0 · Ray
ip6525t-n.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ip6525t-n.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body… · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json ip6525t-n: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md ip6525t-n: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

IP6525T_N

INJOINIC · DC-DC Converters · ESOP-8

IP6525T_N from INJOINIC, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power ground. Return path for the internal power stage; must be tied to the exposed pad (EPAD) plane for proper thermal and electrical performance.
2 SW output DCDC switching node. Connects to the external buck inductor. Absolute-max SW voltage range is -0.3 V to 40 V.
3 BST passive Bootstrap pin for the high-side gate driver. Connect a bootstrap capacitor between BST and SW (placed close to the IC) to provide the drive voltage for the upper power MOSFET gate.
4 HLED/EN bidirectional Dual-function pin. Default configuration is HLED (fast-charge status LED indicator drive); optionally can be configured as an external Enable (EN) input via factory customization.
5 DM bidirectional USB D- (data minus) line used for fast-charge protocol handshaking (DCP/QC2.0/QC3.0/FCP/AFC). Absolute-max voltage range -0.3 V to 30 V.
6 DP bidirectional USB D+ (data plus) line used for fast-charge protocol handshaking (DCP/QC2.0/QC3.0/FCP/AFC). Absolute-max voltage range -0.3 V to 30 V.
7 VIN power_in Input supply pin, 9.6 V to 32 V (absolute-max 40 V). Place a decoupling ceramic capacitor (100 nF recommended) close to the IC.
8 VOUT input Output voltage feedback / sense pin. Used by the internal loop to regulate the buck output (3 V-12 V typical) and provide line-drop compensation (~100 mV @ 1 A).
9 EPAD power_in Exposed thermal pad on the bottom of the ESOP-8 package. Serves as power ground and heatsink; must be soldered to a solid GND copper pour for thermal dissipation.

Key specifications

Parameter Value
Manufacturer INJOINIC
Package ESOP-8
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • IP6525T_N

CAD (KiCad official)

  • Symbol: IP6525T_N
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: ip6525t-n-etched.step / ip6525t-n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ip6525t-n.step / ip6525t-n.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ip6525t-n.step 193 KB You want the bare part, or you mark your own boards.
ip6525t-n-etched.step 1.4 MB You want the part with IP6525T_N already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 372 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: INJOINIC datasheet (11 pp, sha256 1376a6951cb2f147, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF