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IKCM15H60GA
Public Made by Adomby adom
Infineon Technologies Motor Driver ICs, DIP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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IKCM15H60GA
Infineon Technologies · Motor Driver ICs · DIP-24
IKCM15H60GA from Infineon Technologies, in a DIP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS(U) | power_in | U-phase high side floating IC supply offset voltage, which the datasheet says withstands negative voltage of -50V transiently relative to VSS. |
| 2 | VB(U) | power_in | U-phase high side floating IC supply voltage, with a recommended VBS range of 13.5V to 18.5V referenced to VS. |
| 3 | VS(V) | power_in | V-phase high side floating IC supply offset voltage, which the datasheet says withstands negative voltage of -50V transiently relative to VSS. |
| 4 | VB(V) | power_in | V-phase high side floating IC supply voltage, with a recommended VBS range of 13.5V to 18.5V referenced to VS. |
| 5 | VS(W) | power_in | W-phase high side floating IC supply offset voltage, which the datasheet says withstands negative voltage of -50V transiently relative to VSS. |
| 6 | VB(W) | power_in | W-phase high side floating IC supply voltage, with a recommended VBS range of 13.5V to 18.5V referenced to VS. |
| 7 | HIN(U) | input | U-phase high side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 8 | HIN(V) | input | V-phase high side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 9 | HIN(W) | input | W-phase high side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 10 | LIN(U) | input | U-phase low side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 11 | LIN(V) | input | V-phase low side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 12 | LIN(W) | input | W-phase low side gate driver input with positive logic, LSTTL and CMOS compatible down to 3.3V outputs, and a 5V maximum recommended input voltage. |
| 13 | VDD | power_in | Low side control supply powering both the input logic and the output power stage, with a recommended range of 14.5V to 18.5V and under-voltage shutdown below 10.4V typical. |
| 14 | VFO | output | Fault output and direct NTC temperature monitor that is open drain and requires an external pull-up resistor, indicating under-voltage at VDD or an ITRIP over-current trip. |
| 15 | ITRIP | input | Over current shutdown input with a comparator threshold of typ. 0.47V referenced to VSS, a 0 to 5V recommended input range and a typical 530ns input noise filter. |
| 16 | VSS | power_in | Low side control negative supply and logic reference, with VSS to N voltage limited to -5V to 5V including surge. |
| 17 | NW | passive | W-phase low side emitter made available for phase current measurement, to be kept as short as possible to VSS. |
| 18 | NV | passive | V-phase low side emitter made available for phase current measurement, to be kept as short as possible to VSS. |
| 19 | NU | passive | U-phase low side emitter made available for phase current measurement, to be kept as short as possible to VSS. |
| 20 | W | output | Motor W-phase output connected to the high side emitter and low side collector of the W leg, rated for up to 15A output current. |
| 21 | V | power_in | Motor V-phase output connected to the high side emitter and low side collector of the V leg, rated for up to 15A output current. |
| 22 | U | output | Motor U-phase output connected to the high side emitter and low side collector of the U leg, rated for up to 15A output current. |
| 23 | P | power_in | Positive DC bus input to the high side IGBTs, with the datasheet stating the bus voltage must not exceed 450V (VPN maximum). |
| 24 | NC | unconnected | No connection; the datasheet specifies this pin is not connected internally. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | DIP-24 |
| Category | Power Management ICs |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | Tstg | -40 | 125 | °C | 7 | ||
| Isolation test voltage | VISOL | 2000 | V | RMS, f = 60Hz, t = 1min | 7 | ||
| Operating case temperature range | TC | -40 | 125 | °C | Refer to Figure 6 | 7 | |
| Max. blocking voltage | VCES | 600 | V | IC = 250µA | 7 | ||
| DC link supply voltage of P-N | VPN | 450 | V | Applied between P-N | 7 | ||
| DC link supply voltage (surge) of P-N | VPN(surge) | 500 | V | Applied between P-N | 7 | ||
| Output current | IC | -15 | 15 | A | TC = 25°C, TJ < 150°C | 7 | |
| Output current | IC | -10 | 10 | A | TC = 80°C, TJ < 150°C | 7 | |
| Maximum peak output current | IC(peak) | -24 | 24 | A | less than 1ms | 7 | |
| Short circuit withstand time | tSC | 5 | µs | VDC ≤ 400V, TJ = 150°C | 7 | ||
| Power dissipation per IGBT | Ptot | 25.2 | W | 7 | |||
| Operating junction temperature range | TJ | -40 | 150 | °C | 7 | ||
| Single IGBT thermal resistance, junction-case | RthJC | 4.96 | K/W | 7 | |||
| Single diode thermal resistance, junction-case | RthJCD | 5.41 | K/W | 7 | |||
| Module supply voltage | VDD | -1 | 20 | V | 7 | ||
| High side floating supply voltage (VB vs. VS) | VBS | -1 | 20 | V | 7 | ||
| Input voltage LIN, HIN, ITRIP | VIN | -1 | 10 | V | 7 | ||
| Input voltage ITRIP | VITRIP | -1 | 10 | V | 7 | ||
| Switching frequency | fPWM | 20 | kHz | 7 | |||
| DC link supply voltage of P-N | VPN | 0 | 450 | V | 8 | ||
| High side floating supply voltage (VB vs. VS) | VBS | 13.5 | 18.5 | V | 8 | ||
| Low side supply voltage | VDD | 14.5 | 16 | 18.5 | V | 8 | |
| Control supply variation | ΔVBS | -1 | 1 | V/µs | 8 | ||
| Logic input voltages LIN, HIN, ITRIP | VIN | 0 | 5 | V | 8 | ||
| Between VSS - N (including surge) | VSS | -5 | 5 | V | 8 | ||
| Collector-Emitter saturation voltage | VCE(sat) | 1.9 | 2.8 | V | IC = 10A, TJ = 25°C | 9 | |
| Collector-Emitter saturation voltage | VCE(sat) | 2.4 | V | IC = 10A, TJ = 150°C | 9 | ||
| Diode forward voltage | VF | 1.75 | 2.4 | V | IF= 10A, TJ = 25°C | 9 | |
| Diode forward voltage | VF | 1.8 | V | IF= 10A, TJ = 150°C | 9 | ||
| Collector-Emitter leakage current | ICES | 1 | mA | VCE = 600V | 9 | ||
| Logic "1" input voltage (LIN, HIN) | VIH | 2.1 | 2.5 | V | 9 | ||
| Logic "0" input voltage (LIN, HIN) | VIL | 0.7 | 0.9 | V | 9 | ||
| ITRIP positive going threshold | VIT,TH+ | 400 | 470 | 540 | mV | 9 | |
| ITRIP input hysteresis | VIT,HYS | 40 | 70 | mV | 9 | ||
| VDD supply under voltage positive going threshold | VDDUV+ | 10.8 | 12.1 | 13 | V | 9 | |
| VBS supply under voltage positive going threshold | VBSUV+ | 10.8 | 12.1 | 13 | V | 9 | |
| VDD supply under voltage negative going threshold | VDDUV- | 9.5 | 10.4 | 11.2 | V | 9 | |
| VBS supply under voltage negative going threshold | VBSUV- | 9.5 | 10.4 | 11.2 | V | 9 | |
| VDD supply under voltage lockout hysteresis | VDDUVH | 1 | 1.7 | V | 9 | ||
| VBS supply under voltage lockout hysteresis | VBSUVH | 1 | 1.7 | V | 9 | ||
| Input clamp voltage (HIN, LIN, ITRIP) | VINCLAMP | 9 | 10.1 | 12.5 | V | Iin=4mA | 9 |
| Quiescent VBx supply current (VBx only) | IQBS | 300 | 500 | µA | HIN = 0V | 9 | |
| Quiescent VDD supply current (VDD only) | IQDD | 370 | 900 | µA | LIN = 0V, HINX = 5V | 9 | |
| Input bias current | IIN+ | 1 | 1.5 | mA | VIN = 5V | 9 | |
| Input bias current | IIN- | 2 | µA | VIN = 0V | 9 | ||
| ITRIP input bias current | IITRIP+ | 65 | 150 | µA | VITRIP = 5V | 9 | |
| VFO input bias current | IFO | 60 | µA | VFO = 5V, VITRIP = 0V | 9 | ||
| VFO output voltage | VFO | 0.5 | V | IFO = 10mA, VITRIP = 1V | 9 | ||
| Fault clear time after ITRIP-fault | tFLTCLR | 40 | 65 | 200 | µs | VITRIP = 1V | 10 |
| Deadtime between low side and high side | DTPWM | 0.5 | µs | 10 | |||
| Repetitive peak reverse voltage | VRRM | 600 | V | 10 | |||
| Resistor | RNTC | 85 | kΩ | TNTC = 25°C | 11 | ||
| B-constant of NTC | B(25/100) | 4092 | K | 11 | |||
| Deadtime of gate drive circuit | DTIC | 380 | ns | 10 | |||
| Short circuit propagation delay time | tSCP | 1440 | ns | From VIT,TH+ to 10% ISC | 10 | ||
| Input filter time ITRIP | tITRIPmin | 530 | ns | VITRIP = 1V | 10 |
CAD (KiCad official)
- Symbol:
IKCM15H60GA - Footprint:
Package_DIP:DIP-24_W7.62mm - 3D model: DIP-24 (KiCad packages3D, STEP)
- 3D model files:
ikcm15h60ga-etched.step/ikcm15h60ga-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ikcm15h60ga.step/ikcm15h60ga.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (17 pp, sha256
6bc4fa980fdababb, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).