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docs ice3pcs01g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ice3pcs01g-etched.fit.json ice3pcs01g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ice3pcs01g-etched.glb ice3pcs01g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ice3pcs01g-etched.step ice3pcs01g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ice3pcs01g.glb Publish 0.1.0 · Ray
ice3pcs01g.kicad_mod Publish 0.1.0 · Ray
ice3pcs01g.kicad_sym Publish 0.1.0 · Ray
ice3pcs01g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ice3pcs01g.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json ice3pcs01g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md ice3pcs01g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

ICE3PCS01G

Infineon · AC-DC Controllers and Regulators · SOIC-14

ICE3PCS01G from Infineon, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOFO output Boost Follower setting. An external DC voltage on this pin indicates the PWM output power level; used to select the boost follower low step. Set with an external resistor divider (R_BOFO1..2, ~200 kΩ).
2 ISENSE input Current Sense Input. Senses the voltage drop across the external shunt resistor R_SHUNT for average current control loop and peak current limitation. A series resistor R_CS (~50 Ω) is recommended in series to limit inrush current into the pin.
3 SGND power_in Signal Ground. Ground reference of the IC signal-level circuitry; kept separate from the power/gate switching ground (PGND).
4 ICOMP output Current Loop Compensation. Low-pass filter/compensation node for the current control loop; external capacitor C_ICOMP (~4.7 nF/25 V) to SGND integrates the OTA6 output and averages the current sense signal. Internally shorted to 5 V in standby.
5 FREQ input Switching Frequency Setting. Set the operating frequency (21 kHz to 100 kHz) via a resistor R_FREQ to SGND (e.g. 67 kΩ → ~65 kHz). Also serves as the external synchronization input when driven by an external pulse >2.5 V.
6 VB_OK output Bulk Voltage OK signal. Internally pulled up to 5 V once the bulk voltage exceeds 95% of the rated level; pulled to ground when VSENSE falls below the VBTHL_EN threshold. Can be used to enable the downstream PWM IC or an inrush relay.
7 VBTHL_EN input PFC Enable Function / VB_OK turn-off threshold. An external reference sets the VB_OK signal turn-off threshold. Pulling this pin below 0.5 V shuts down the IC.
8 VREF power_out Voltage Reference. 5 V internal regulator output with minimum 5 mA sourcing capability; bypass with ~100 nF/25 V to SGND.
9 BOP input Brownout Protection. Monitors the AC input voltage for brownout protection and line-range selection via an external RC divider from the rectified AC (BOP threshold >1.25 V for start-up).
10 OVP input Over Voltage Protection. Additional resistive divider from bulk voltage to SGND sets the secondary over-voltage protection threshold to ensure safe system operation.
11 VSENSE input Bulk Voltage Sense. Connected via a resistive divider to the boost output bulk voltage; feeds the sigma-delta ADC (2.5 V internal reference, 3.55 kHz sampling) used for voltage regulation, over-voltage and open-loop protection.
12 VCC power_in IC Supply Voltage. Main supply for the IC section, up to 25 V. UVLO turn-on at 12.0 V (with VSENSE >0.5 V and BOP >1.25 V); turn-off below 11 V. Typical operating current 6.7 mA, standby ~1.4 mA.
13 GATE output Gate Drive Output for the external PFC boost MOSFET. Gate drive voltage is clamped at 15 V (typical); series resistor R_GATE ~3.3 Ω recommended.
14 PGND power_in Power Ground / Gate Switching Ground. Return path for the gate driver current; kept separate from SGND for noise isolation.

Key specifications

Parameter Value
Manufacturer Infineon
Package SOIC-14
Category PMIC
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • ICE3PCS01GG

CAD (KiCad official)

  • Symbol: ICE3PCS01G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: ice3pcs01g-etched.step / ice3pcs01g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ice3pcs01g.step / ice3pcs01g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ice3pcs01g.step 195 KB You want the bare part, or you mark your own boards.
ice3pcs01g-etched.step 2.5 MB You want the part with ICE3PCS01G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 624 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon datasheet (22 pp, sha256 24cecdf8968137bc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF