component
HX65HVD230-S
Public Made by Adomby adom
ZHHXDZ CAN Transceivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| hx65hvd230-s-etched.glb | 7d ago |
| hx65hvd230-s-etched.step | 7d ago |
| hx65hvd230-s-hero.glb | 7d ago |
| hx65hvd230-s-hero.overlay.json | 7d ago |
| hx65hvd230-s.glb | 7d ago |
| hx65hvd230-s.kicad_mod | 7d ago |
| hx65hvd230-s.kicad_sym | 7d ago |
| hx65hvd230-s.lbr | 7d ago |
| hx65hvd230-s.step | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
HX65HVD230-S
ZHHXDZ · CAN Transceivers · SOP-8
HX65HVD230-S from ZHHXDZ, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | input | CAN transmit data input (also called TXD, driver input): low for dominant bus state and high for recessive bus state. The datasheet limits MCU-side port voltage to -0.5 V to VCC+0.5 V. |
| 2 | GND | power_in | Ground connection for the transceiver; all voltages are referenced to this pin. |
| 3 | VCC | power_in | Transceiver 3.3 V supply pin; operating range is 3 V to 3.6 V and the absolute maximum rating is -0.3 V to +6 V. |
| 4 | R | output | CAN receive data output (also called RXD, driver output): low for dominant bus state and high for recessive bus state. The MCU-side port voltage is limited to -0.5 V to VCC+0.5 V and the receiver output current to -11 mA to +11 mA. |
| 5 | Vref | power_out | Vcc/2 reference voltage output; it stays within 0.45VCC to 0.55VCC for -5 µA < Iref < 5 µA and within 0.4VCC to 0.6VCC for -50 µA < Iref < 50 µA. |
| 6 | CANL | bidirectional | Low-level CAN bus line; the bus-side input voltage is limited to -18 V to 18 V, and pins 6 and 7 withstand transients of -25 V to +25 V (100 Ω test, see Figure 9). |
| 7 | CANH | bidirectional | High-level CAN bus line; the bus-side input voltage is limited to -18 V to 18 V, and pins 6 and 7 withstand transients of -25 V to +25 V (100 Ω test, see Figure 9). |
| 8 | RS | input | Mode select pin: strongly pulled to GND selects high-speed mode, strongly pulled to VCC selects standby (low-power) mode, and a 10 kΩ to 100 kΩ resistor to GND selects slope-control mode; standby is entered when the voltage exceeds 0.75 VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ZHHXDZ |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 供电电压 | Vcc | 3 | 3.6 | V | 1 | ||
| 最大传输速率 | 1/tbit | 1 | Mbaud | 非归零码 | 1 | ||
| CANH、CANL 引脚电压 | Vcan | -16 | 16 | V | 1 | ||
| 总线差分电压 | Vdiff | 1.5 | 3 | V | 1 | ||
| 环境温度 | Tamb | -40 | 125 | ℃ | 1 | ||
| 电源电压 | VCC | -0.3 | 6 | V | 2 | ||
| MCU 侧端口电压 D,R | -0.5 | V | max printed as VCC+0.5 (not computed) | 2 | |||
| 总线侧输入电压 CANL,CANH | -18 | 18 | V | 2 | |||
| 6,7 号引脚瞬态电压 | Vtr | -25 | 25 | V | 100Ω测试(见图 9) | 2 | |
| 接收器输出电流 | IO | -11 | 11 | mA | 2 | ||
| 存储工作温度范围 | -40 | 150 | ℃ | 2 | |||
| 焊接温度范围 | 300 | ℃ | 2 | ||||
| 总线发送器输出电压(显性)CANH | VO(D) | 2.45 | V | VI=0V,RS=0V,RL=60Ω; max printed as VCC | 3 | ||
| 总线发送器输出电压(显性)CANL | VO(D) | 0.5 | 1.25 | V | VI=0V,RS=0V,RL=60Ω | 3 | |
| 差分输出电压(显性) | VOD(D) | 1.5 | 2 | 3 | V | VI=0V,RS=0V,RL=60Ω | 3 |
| 差分输出电压(显性) | VOD(D) | 1.2 | 2 | 3 | V | VI=0V,RL=60Ω,RS=0V | 3 |
| 输出电压(隐性)CANH | VO(R) | 2.3 | V | VI=3V,RS=0V,RL=60Ω | 3 | ||
| 输出电压(隐性)CANL | VO(R) | 2.3 | V | VI=3V,RS=0V,RL=60Ω | 3 | ||
| 差分输出电压(隐性) | VOD(R) | -0.12 | 0.012 | V | VI=3V, RS=0V | 3 | |
| 差分输出电压(隐性)无负载 | VOD(R) | -0.5 | 0.05 | V | VI=3V, RS=0V,NO LOAD | 3 | |
| 高电压输入电流 | IIH | -30 | μA | VI=2V | 3 | ||
| 低电压输入电流 | IIL | -30 | μA | VI=0.8V | 3 | ||
| 短路输出电流 | IOS | -250 | mA | CANH=-2V | 3 | ||
| 短路输出电流 | IOS | 250 | mA | CANL=7V | 3 | ||
| 供电电流(待机) | ICC | 650 | 950 | μA | 待机 | 3 | |
| 供电电流(显性) | 10 | 17 | mA | VI=0V(显性),无负载 | 3 | ||
| 供电电流(隐性) | 10 | 17 | mA | VI=VCC(隐性),无负载 | 3 | ||
| 传播延迟(低到高) | tPLH | 35 | 85 | ns | R=0,即短路(见图 4) | 3 | |
| 传播延迟(低到高) | tPLH | 70 | 125 | ns | R=10 kΩ | 3 | |
| 传播延迟(高到低) | tPHL | 70 | 120 | ns | R=0,即短路(见图 4) | 3 | |
| 传播延迟(高到低) | tPHL | 130 | 180 | ns | R=10 kΩ | 3 | |
| 传播延迟对称性 | tsk(p) | 35 | ns | R=0,即短路(见图 4) | 3 | ||
| 传播延迟对称性 | tsk(p) | 60 | ns | R=10 kΩ | 4 | ||
| 传播延迟对称性 | tsk(p) | 370 | ns | R=100 kΩ | 4 | ||
| 差分输出上升时间 | tr | 25 | 50 | 100 | ns | R=0,即短路(见图 4) | 4 |
| 差分输出上升时间 | tr | 80 | 120 | 160 | ns | R=10 kΩ | 4 |
| 差分输出下降时间 | tf | 40 | 55 | 80 | ns | R=0,即短路(见图 4) | 4 |
| 差分输出下降时间 | tf | 80 | 125 | 150 | ns | R=10 kΩ | 4 |
| 接收器正阈值 | VIT+ | 750 | 900 | mV | 见表 1 | 4 | |
| 接收器负阈值 | VIT- | 500 | 650 | mV | 见表 1 | 4 | |
| 高电平输出电压 | VOH | 2.4 | V | -6V<VID<500mV, Io=-8mA(见图 5) | 4 | ||
| 低电平输出电压 | VOL | 0.4 | V | 900mV<VID<6V, Io=8mA(见图 5) | 4 | ||
| 总线输入电流 | Ii | 100 | 350 | μA | VIH=7V,VCC=0V | 4 | |
| 总线输入电流 | Ii | 100 | 250 | μA | VIH=7V,VCC=3.3V | 4 | |
| 总线输入电流 | Ii | -100 | -20 | μA | VIH=-2V,VCC=0V | 4 | |
| 总线输入电流 | Ii | -200 | -30 | μA | VIH=-2V,VCC=3.3V | 4 | |
| 总线输入电阻 | Ri | 20 | 35 | 50 | KΩ | ISO 11898-2 对应标准 | 4 |
| 差分输入电阻 | Rdiff | 40 | 100 | KΩ | ISO 11898-2 对应标准 | 4 | |
| 接收器传播延时(低-高) | tpLH | 35 | 50 | ns | 见图 6 | 5 | |
| 接收器传播延时(高-低) | tpHL | 35 | 50 | ns | 见图 6 | 5 | |
| 脉冲偏移 | tsk | 10 | ns | /tpHL − tpLH/ | 5 | ||
| 环路延迟 1,驱动器输入到接收器输出,隐性到显性 | t(LOOP1) | 70 | 115 | ns | R=0,即短路(见图 8) | 5 | |
| 环路延迟 1,驱动器输入到接收器输出,隐性到显性 | t(LOOP1) | 105 | 175 | ns | R=10 kΩ | 5 | |
| 环路延迟 2,驱动器输入到接收器输出,显性到隐性 | t(LOOP2) | 100 | 135 | ns | R=0,即短路(见图 8) | 5 | |
| 环路延迟 2,驱动器输入到接收器输出,显性到隐性 | t(LOOP2) | 155 | 185 | ns | R=10 kΩ | 5 | |
| 待机到唤醒时间 | TWAKE | 0.55 | 1.5 | us | RS加入方波(见图 7) | 6 | |
| 高速模式输入电流 | IRS | -450 | 0 | μA | VRS<1V | 6 | |
| 掉电漏电流 | Ioff | -250 | 250 | μA | Vcc=0V,VCANH=VCANL=5V | 6 | |
| 显性功耗 | 50 | 70 | mA | VI=0V, RS=0V, LOAD=60Ω | 6 | ||
| 隐性功耗 | 6 | 10 | mA | VI=VCC, RS=0V, NO LOAD | 6 |
CAD (KiCad official)
- Symbol:
HX65HVD230-S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hx65hvd230-s-etched.step/hx65hvd230-s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hx65hvd230-s.step/hx65hvd230-s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ZHHXDZ datasheet (12 pp, sha256
0bd38b46ace059fc, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).