# HG1302ZN

**HGSEMI** · Real Time Clocks · DIP-8

HG1302ZN from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC2 | power_in | Main supply pin, rated 2.0 V to 5.5 V; the device is powered from VCC2 when VCC2 is more than 0.2 V above VCC1. |
| 2 | X1 | passive | Connects directly to one terminal of a 32.768 kHz crystal, and the selected crystal's specified load capacitance should be 6 pF. |
| 3 | X2 | passive | Connects directly to the other terminal of the 32.768 kHz crystal, and the selected crystal's specified load capacitance should be 6 pF. |
| 4 | GND | power_in | Ground reference pin for the device. |
| 5 | RST | input | Driving RST high enables and starts all data transfers, and driving it low aborts them and tri-states I/O; RST must be logic 0 before VCC reaches 2.5 V at power-up, and SCLK must be logic 0 when RST is driven high. |
| 6 | I/O | bidirectional | Serial data input/output: data is latched on SCLK rising edges during writes and driven on SCLK falling edges during reads, and the pin is high impedance when RST is low. |
| 7 | SCLK | input | Serial clock input that synchronizes command and data shifting on I/O; it must be logic 0 when RST is driven to logic 1. |
| 8 | VCC1 | power_in | Backup supply pin, rated 2.0 V to 5.5 V, that powers the device when VCC2 is not higher than VCC1 by more than 0.2 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Clock/Timing |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 引脚对地电压 | VP | -0.5 |  | 7 | V |  | 3 |
| 工作温度 (HG1302Z / ZN package) | TA | -40 |  | 85 | ℃ | HG1302Z variant | 3 |
| 贮存温度 | TS | -55 |  | 125 | ℃ |  | 3 |
| 焊接温度 | TH |  |  | 260 | ℃ | 10 秒 | 3 |
| 供给电源电压 | VCC1, VCC2 | 2 |  | 5.5 | V | TA=0℃～70℃ | 3 |
| 逻辑1输入电压 | VIH | 2 |  |  | V | TA=0℃～70℃ | 3 |
| 逻辑0输入电压 | VIL | -0.3 |  | 0.3 | V | VCC=2.0V | 3 |
| 逻辑0输入电压 | VIL | -0.3 |  | 0.8 | V | VCC=5V | 3 |
| 输入电容 | CI |  |  | 10 | pF | TA=25℃ | 3 |
| I/O电容 | CI/O |  |  | 15 | pF | TA=25℃ | 3 |
| 晶体振荡器电容 | CX |  |  | 6 | pF | TA=25℃ | 3 |
| 输入电流 | ILI |  |  | 500 | μA | 0℃至70℃；VCC=2.5V至5.5V | 3 |
| I/O 漏电流 | ILO |  |  | 500 | μA | 0℃至70℃；VCC=2.5V至5.5V | 3 |
| 逻辑1输出电压 | VOH | 1.6 |  |  | V | VCC=2.5V | 3 |
| 逻辑1输出电压 | VOH | 2.4 |  |  | V | VCC=5V | 3 |
| 逻辑0输出电压 | VOL |  |  | 0.4 | V | VCC=2.5V | 3 |
| 供电电流 | ICC1A |  |  | 0.4 | mA | VCC1=2.5V | 3 |
| 供电电流 | ICC1A |  |  | 1.2 | mA | VCC1=5V | 3 |
| 时间保持电流 | ICC1T |  |  | 0.3 | μA | VCC1=2.5V | 3 |
| 时间保持电流 | ICC1T |  |  | 1 | μA | VCC1=5V | 3 |
| 静态电流 | ICC1S |  |  | 100 | nA | VCC1=2.5V | 3 |
| 供电电流 | ICC2A |  |  | 0.425 | mA | VCC2=2.5V | 4 |
| 供电电流 | ICC2A |  |  | 1.28 | mA | VCC2=5V | 4 |
| 时间保持电流 | ICC2T |  |  | 25.3 | μA | VCC2=2.5V | 4 |
| 时间保持电流 | ICC2T |  |  | 81 | μA | VCC2=5V | 4 |
| 静态电流 | ICC2S |  |  | 25 | μA | VCC2=2.5V | 4 |
| 静态电流 | ICC2S |  |  | 80 | μA | VCC2=5V | 4 |
| 涓流充电二极管压降 | VTD |  |  | 0.7 | V |  | 4 |
| CLK到RST保持 | tcch | 240 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK到RST保持 | tcch | 60 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| RST无效 | tcwh | 4 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| RST无效 | tcwh | 1 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| RST到I/O高阻 | tcdz |  |  | 280 | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| RST到I/O高阻 | tcdz |  |  | 70 | ns | VCC=5V; TA=0℃至70℃ | 4 |
| SCLK到I/O高阻 | tccz |  |  | 280 | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| SCLK到I/O高阻 | tccz |  |  | 70 | ns | VCC=5V; TA=0℃至70℃ | 4 |
| Data到CLK建立 | tdc | 200 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| Data到CLK建立 | tdc | 50 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| CLK到Data保持 | tcdh | 280 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK到Data保持 | tcdh | 70 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| CLK到Data延时 | tcdd |  |  | 800 | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK到Data延时 | tcdd |  |  | 200 | ns | VCC=5V; TA=0℃至70℃ | 4 |
| CLK低 | tcl | 1000 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK低 | tcl | 250 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| CLK高 | tch | 1000 |  |  | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK高 | tch | 250 |  |  | ns | VCC=5V; TA=0℃至70℃ | 4 |
| CLK频率 | tclk |  |  | 0.5 | MHz | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK频率 | tclk |  |  | 2 | MHz | VCC=5V; TA=0℃至70℃ | 4 |
| CLK上升和下降时间 | tr, tf |  |  | 2000 | ns | VCC=2.5V; TA=0℃至70℃ | 4 |
| CLK上升和下降时间 | tr, tf |  |  | 500 | ns | VCC=5V; TA=0℃至70℃ | 4 |
| RST到CLK建立 | tCC | 4 |  |  | µs | VCC=2.5V; TA=0℃至70℃ | 4 |
| RST到CLK建立 | tCC | 1 |  |  | µs | VCC=5V; TA=0℃至70℃ | 4 |

## CAD (KiCad official)

- Symbol: `HG1302ZN`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `hg1302zn-etched.step` / `hg1302zn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hg1302zn.step` / `hg1302zn.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603087735574458368) (14 pp, sha256 `313dc8a655711ee6`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hg1302zn-datasheet.pdf)