HG1302ZM

{
  "schema_version": 1,
  "type": "component",
  "slug": "hg1302zm",
  "title": "HG1302ZM",
  "brief": "HGSEMI Real Time Clocks, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "clock-timing",
    "hg1302zm",
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  "component": {
    "mpn": "HG1302ZM",
    "manufacturer": "HGSEMI",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Clock/Timing",
    "subcategory": "Real Time Clocks",
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      "model_3d_step_plain": "hg1302zm.step",
      "lbr": "hg1302zm.lbr"
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    "distributor_links": {
      "lcsc": "C5310789"
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      "source": "Component Ocean /api/assign-pns",
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        "status": "quota"
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      {
        "number": "1",
        "name": "VCC2",
        "type": "power_in",
        "description": "Main supply pin for the dual-supply configuration; the chip runs from VCC2 when it exceeds VCC1 by more than 0.2V, and supply range is 2.0V to 5.5V."
      },
      {
        "number": "2",
        "name": "X1",
        "type": "passive",
        "description": "Connection for the 32.768kHz crystal, which connects directly to pins 2 and 3 and requires a specified load capacitance of 6pF."
      },
      {
        "number": "3",
        "name": "X2",
        "type": "passive",
        "description": "Connection for the 32.768kHz crystal, which connects directly to pins 2 and 3 and requires a specified load capacitance of 6pF."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "5",
        "name": "RST",
        "type": "input",
        "description": "Reset/enable input that must be driven high to start any data transfer; driving it low aborts the transfer and puts I/O in high impedance, and it must be logic 0 before VCC reaches 2.5V at power-up."
      },
      {
        "number": "6",
        "name": "I/O",
        "type": "bidirectional",
        "description": "Serial data input/output; data is valid on the SCLK rising edge for writes and output on the falling edge for reads, and the pin goes high-impedance when RST is low."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input that must be logic 0 when RST is driven to logic 1."
      },
      {
        "number": "8",
        "name": "VCC1",
        "type": "power_in",
        "description": "Backup supply pin for battery backup of the clock and RAM data in dual-supply systems, with supply range 2.0V to 5.5V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
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        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
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        ],
        "pages_sent": 14,
        "cost_usd": 0.0499,
        "at": "2026-10-18T14:10:30"
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        "sha256": "313dc8a655711ee6",
        "source_tier": "lcsc"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
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        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
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      "Manufacturer": "HGSEMI",
      "Package": "SOP-8",
      "Category": "Clock/Timing",
      "Pins": "8"
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