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HC32L170JATH-LQ48

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HC32L170JATH-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32L170JATH-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCAP power_out Internal LDO core-supply output for internal circuits only; it requires an external decoupling capacitor of at least 1 µF.
2 PC13 bidirectional General-purpose I/O PC13 with RTC_1HZ and TIM3_CH1B alternate functions, and LVD0 voltage-detection input.
3 XTLI/PC14 bidirectional Port PC14 that doubles as the low-speed crystal oscillator input XTLI for a 32.768 kHz crystal.
4 XTLO/PC15 bidirectional Port PC15 that doubles as the low-speed crystal oscillator output XTLO for a 32.768 kHz crystal.
5 XTHI/PF00 bidirectional Port PF00 that doubles as the high-speed crystal oscillator input XTHI for a 4-32 MHz crystal, with I2C0_SDA and UART1_TXD alternate functions.
6 XTHO/PF01 bidirectional Port PF01 that doubles as the high-speed crystal oscillator output XTHO for a 4-32 MHz crystal, with I2C0_SCL, TIM4_CHB and UART1_RXD alternate functions.
7 RESETB input Reset input with CMOS Schmitt-trigger hysteresis of 200 mV and a non-disconnectable weak pull-up of about 80 kΩ; input pulses shorter than 100 ns are filtered.
8 AVSS power_in Analog ground; it must be connected to the same ground system as DVSS.
9 AVCC power_in Analog supply, operating range 1.8-5.5 V; it must be at the same voltage as DVCC and needs its own decoupling capacitor placed close to the pin.
10 PA00 bidirectional Port PA00 with UART1_CTS, LPUART1_TXD, TIM0_ETR, VC0_OUT, TIM1_CHA, TIM3_ETR and TIM0_CHA alternate functions, and ADC input AIN0.
11 PA01 bidirectional Port PA01 with UART1_RTS, LPUART1_RXD, TIM0_CHB, TIM1_ETR, TIM1_CHB, HCLK_OUT and SPI1_MOSI alternate functions, and ADC input AIN1.
12 PA02 bidirectional Port PA02 with UART1_TXD, TIM0_CHA, VC1_OUT, TIM1_CHA, TIM2_CHA, PCLK_OUT and SPI1_MISO alternate functions, and ADC input AIN2.
13 PA03 bidirectional Port PA03 with UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A and TIM5_CHA alternate functions, and ADC input AIN3.
14 PA04 bidirectional Port PA04 with SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT and TIM3_CH2B alternate functions, and ADC input AIN4, DAC_OUT and OPA_OUT0 analog functions.
15 PA05 bidirectional Port PA05 with SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT and XTH_OUT alternate functions.
16 PA06 bidirectional Port PA06 with SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT, TIM3_GATE and LPUART0_CTS alternate functions.
17 PA07 bidirectional Port PA07 with SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT and TIM4_CHB alternate functions.
18 PB00 bidirectional Port PB00 with PCA_CH2, TIM3_CH1B, LPUART0_TXD, TIM5_CHB, RCH_OUT, RCL_OUT and PLL_OUT alternate functions, and ADC input AIN (per pin table).
19 PB01 bidirectional Port PB01 with PCA_CH3, PCLK_OUT, TIM3_CH2B, TIM6_CHB, LPUART0_RTS, VC2_OUT and TCLK_OUT alternate functions.
20 PB02 bidirectional Port PB02 with LPTIM_TOG, PCA_ECI, LPUART1_TXD, TIM4_CHA, TIM1_BK, TIM0_BK and TIM2_BK alternate functions.
21 PB10 bidirectional Port PB10 with I2C1_SCL, SPI1_SCK, TIM1_CHA, LPUART0_TXD, TIM3_CH1A, LPUART1_RTS and UART1_RTS alternate functions.
22 PB11 bidirectional Port PB11 with I2C1_SDA, TIM1_CHB, LPUART0_RXD, TIM2_GATE, TIM6_CHA, LPUART1_CTS and UART1_CTS alternate functions.
23 DVSS power_in Digital ground for the core and I/O; it must be connected to the system ground.
24 DVCC power_in Digital supply, operating range 1.8-5.5 V, which must match AVCC and has a decoupling capacitor placed close to the pin.
25 PB12 bidirectional Port PB12 with SPI1_CS, TIM3_BK, LPUART0_TXD, TIM0_BK, LPUART0_RTS and TIM6_CHA alternate functions.
26 PB13 bidirectional Port PB13 with SPI1_SCK, I2C1_SCL, TIM3_CH0B, LPUART0_CTS, TIM1_CHA, TIM1_GATE and TIM6_CHB alternate functions.
27 PB14 bidirectional Port PB14 with SPI1_MISO, I2C1_SDA, TIM3_CH1B, TIM0_CHA, RTC_1HZ, LPUART0_RTS and TIM1_BK alternate functions.
28 PB15 bidirectional Port PB15 with SPI1_MOSI, TIM3_CH2B, TIM0_CHB, TIM0_GATE and LPUART1_RXD alternate functions.
29 PA08 bidirectional Port PA08 with UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA and TIM3_BK alternate functions.
30 PA09 bidirectional Port PA09 with UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT and TIM5_CHA alternate functions.
31 PA10 bidirectional Port PA10 with UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT and TIM6_CHA alternate functions.
32 PA11 bidirectional Port PA11 with UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO and TIM4_CHB alternate functions.
33 PA12 bidirectional Port PA12 with UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT, SPI0_MOSI and PCNT_S0 alternate functions.
34 PA13/SWDIO bidirectional Port PA13 that serves as the SWD debug data pin SWDIO, with IR_OUT, UART0_RXD, LVD_OUT, TIM3_ETR, RTC_1HZ, PCNT_S1 and VC2_OUT alternate functions.
35 PF06 bidirectional Port PF06 with I2C1_SCL, LPUART1_CTS and UART0_CTS alternate functions.
36 PF07 bidirectional Port PF07 with I2C1_SDA, LPUART1_RTS and UART0_RTS alternate functions.
37 PA14/SWCLK bidirectional Port PA14 that serves as the SWD debug clock pin SWCLK, with UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT and PLL_OUT alternate functions.
38 PA15 bidirectional Port PA15 with SPI0_CS, UART1_RXD, LPUART1_RTS, TIM0_ETR, TIM0_CHA and TIM3_CH1A alternate functions.
39 PB03 bidirectional Port PB03 with SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, LPTIM_GATE, XTL_OUT and XTH_OUT alternate functions.
40 PB04 bidirectional Port PB04 with SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B and LPTIM_ETR alternate functions.
41 PB05 bidirectional Port PB05 with SPI0_MOSI, TIM1_BK, PCA_CH1, LPTIM_GATE, PCNT_S0 and UART0_RTS alternate functions.
42 PB06 bidirectional Port PB06 with I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA, LPTIM_ETR, TIM3_CH0A and LPTIM_TOG alternate functions.
43 PB07 bidirectional Port PB07 with I2C0_SDA, UART0_RXD, TIM2_CHB, LPUART1_CTS, TIM0_CHB, LPTIM_TOGN and PCNT_S1 alternate functions.
44 BOOT0 input Boot-mode pin sampled at reset: high selects ISP programming mode, and low selects user mode, which runs Flash code and allows SWD programming.
45 PB08 bidirectional Port PB08 with I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, TIM3_CH2A and UART0_TXD alternate functions.
46 PB09 bidirectional Port PB09 with I2C0_SDA, IR_OUT, SPI1_CS, TIM2_CHA, TIM2_CHB and UART0_RXD alternate functions.
47 DVSS power_in Digital ground for the core and I/O; it must be connected to the system ground.
48 DVCC power_in Digital supply, operating range 1.8-5.5 V, which must match AVCC and has a decoupling capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (incl. AVCC and DVCC) VCC - VSS -0.3 5.5 V 49
Input voltage on other pins VIN -0.3 V Printed min VSS-0.3 (min entered as -0.3 referenced to VSS); printed max VCC+0.3 is not a fixed number, so max is null 49
Voltage difference between supply pins /ΔVCCx/ 50 mV 49
Voltage difference between ground pins /VSSx - VSS/ 50 mV 49
Total current through DVCC/AVCC supply lines IVCC 300 mA 49
Total current through VSS ground line IVSS 300 mA 49
Output sink current on any I/O and control pin IIO 25 mA 49
Output current on any I/O and control pin IIO -25 mA 49
Injection current on RESETB pin IINJ(PIN) -5 5 mA 49
Injection current on XTHI and XTLI pins IINJ(PIN) -5 5 mA 49
Injection current on other pins IINJ(PIN) -5 5 mA 49
Total injection current on all I/O and control pins ∑IINJ(PIN) -25 25 mA 49
External input voltage range (LVD) Vex 0 V Printed max is VCC, not a fixed number 53
LVD detection threshold tolerance Vlevel -3.5 3.5 % Applies to every LVD_CR.VTDS setting 0000 to 1111 53
Internal 2.5V reference voltage VREF25 2.475 2.5 2.525 V 常温25°C, 3.3V 54
Internal 2.5V reference voltage VREF25 2.463 2.5 2.525 V -4085°C, 2.85.5V 54
Internal 1.5V reference voltage VREF15 1.485 1.5 1.515 V 常温25°C, 3.3V 54
Internal 1.5V reference voltage VREF15 1.477 1.5 1.519 V -4085°C, 1.85.5V 54
Internal 2.5V and 1.5V reference temperature coefficient TCoeff 120 ppm/°C -40~85°C 54
Supply current IDD, run while(1) in Flash, RCH clock 4M IDD 1000 1430 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, RCH clock 8M IDD 1890 2710 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, RCH clock 16M IDD 3710 5160 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, RCH clock 22.12M IDD 5010 7000 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, RCH clock 24M IDD 5400 7570 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, PLL from RCH4M, 16M IDD 3930 4990 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, PLL from RCH4M, 24M IDD 5480 7080 μA All peripherals ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, PLL from RCH4M, 32M IDD 6590 7640 μA All peripherals ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, PLL from RCH4M, 40M IDD 8100 9470 μA All peripherals ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, PLL from RCH4M, 48M IDD 9610 11200 μA All peripherals ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, all peripherals OFF, RCH 4M IDD 610 990 μA All peripherals OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, all peripherals OFF, RCH 8M IDD 1090 1830 μA All peripherals OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Supply current IDD, run while(1) in Flash, all peripherals OFF, RCH 16M IDD 2080 3350 μA All peripherals OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
LVD detection threshold Vlevel 1.8 V LVD_CR.VTDS=0000 53
LVD detection threshold Vlevel 1.9 V LVD_CR.VTDS=0001 53
LVD detection threshold Vlevel 2 V LVD_CR.VTDS=0010 53
LVD detection threshold Vlevel 2.1 V LVD_CR.VTDS=0011 53
LVD detection threshold Vlevel 2.2 V LVD_CR.VTDS=0100 53
LVD detection threshold Vlevel 2.3 V LVD_CR.VTDS=0101 53
LVD detection threshold Vlevel 2.4 V LVD_CR.VTDS=0110 53
LVD detection threshold Vlevel 2.5 V LVD_CR.VTDS=0111 53
LVD detection threshold Vlevel 2.6 V LVD_CR.VTDS=1000 53
LVD detection threshold Vlevel 2.7 V LVD_CR.VTDS=1001 53
LVD detection threshold Vlevel 2.8 V LVD_CR.VTDS=1010 53
LVD detection threshold Vlevel 2.9 V LVD_CR.VTDS=1011 53
LVD detection threshold Vlevel 3 V LVD_CR.VTDS=1100 53
LVD detection threshold Vlevel 3.1 V LVD_CR.VTDS=1101 53
LVD detection threshold Vlevel 3.2 V LVD_CR.VTDS=1110 53
LVD detection threshold Vlevel 3.3 V LVD_CR.VTDS=1111 53
LVD quiescent current Icomp 0.12 μA 53
LVD response time Tresponse 80 μs 53
LVD setup time Tsetup 400 μs 53
LVD hysteresis voltage Vhyste 40 mV 53
LVD filter time Tfilter 7 μs LVD_debounce=000 53
LVD filter time Tfilter 14 μs LVD_debounce=001 53
LVD filter time Tfilter 28 μs LVD_debounce=010 53
LVD filter time Tfilter 112 μs LVD_debounce=011 53
LVD filter time Tfilter 450 μs LVD_debounce=100 53
LVD filter time Tfilter 1800 μs LVD_debounce=101 53
LVD filter time Tfilter 7200 μs LVD_debounce=110 53
LVD filter time Tfilter 28800 μs LVD_debounce=111 53

CAD (KiCad official)

  • Symbol: HC32L170JATH-LQ48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hc32l170jath-lq48-etched.step / hc32l170jath-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32l170jath-lq48.step / hc32l170jath-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (98 pp, sha256 6c88b764c7b2ca0d, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF