component
HC32F030F8TA-LQ32
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
HC32F030F8TA-LQ32
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
HC32F030F8TA-LQ32 from XHSC, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCAP | power_out | LDO core-supply output for internal circuits only, requires an external decoupling capacitor of at least 1 µF. |
| 2 | XTHI/PD00 | bidirectional | High-speed crystal oscillator input XTHI (4-32 MHz) shared with GPIO PD00, whose alternate functions are I2C0_SDA and UART1_TXD. |
| 3 | XTHO/PD01 | bidirectional | High-speed crystal oscillator output XTHO (4-32 MHz) shared with GPIO PD01, whose alternate functions are I2C0_SCL, TIM4_CHB and UART1_RXD. |
| 4 | RESETB | input | Active-low reset input, CMOS with a non-disconnectable pull-up (about 80 kΩ), VIL up to 0.3VCC and VIH from 0.7VCC. |
| 5 | AVCC | power_in | Analog supply, 1.8-5.5 V, which must be the same voltage as DVCC (at most 300 mV difference is allowed during power-up and operation). |
| 6 | PA00 | bidirectional | GPIO PA00 that also serves ADC input AIN0, comparator inputs VC0/VC1, and UART1_CTS, TIM0, TIM1 and TIM3 functions. |
| 7 | PA01 | bidirectional | GPIO PA01 that also serves ADC input AIN1, comparator inputs, UART1_RTS, TIM0/TIM1 channels, HCLK_OUT and SPI1_MOSI. |
| 8 | PA02 | bidirectional | GPIO PA02 that also serves ADC input AIN2, comparator inputs, VC1_OUT, UART1_TXD, PCLK_OUT and SPI1_MISO. |
| 9 | PA03 | bidirectional | GPIO PA03 with digital alternate functions UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A and TIM5_CHA. |
| 10 | PA04 | bidirectional | GPIO PA04 with alternate functions SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT and TIM3_CH2B. |
| 11 | PA05 | bidirectional | GPIO PA05 with alternate functions SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT and XTH_OUT. |
| 12 | PA06 | bidirectional | GPIO PA06 with alternate functions SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT and TIM3_GATE. |
| 13 | PA07 | bidirectional | GPIO PA07 with alternate functions SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT and TIM4_CHB. |
| 14 | PB00 | bidirectional | GPIO PB00 with alternate functions PCA_CH2, TIM3_CH1B, TIM5_CHB, RCH_OUT, RCL_OUT and PLL_OUT. |
| 15 | PB01 | bidirectional | GPIO PB01 with alternate functions PCA_CH3, PCLK_OUT, TIM3_CH2B and TIM6_CHB. |
| 16 | DVSS | power_in | Digital ground. |
| 17 | DVCC | power_in | Digital supply, 1.8-5.5 V, with a decoupling capacitor placed as close as possible to the pin. |
| 18 | PA08 | bidirectional | GPIO PA08 with alternate functions UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA and TIM3_BK. |
| 19 | PA09 | bidirectional | GPIO PA09 with alternate functions UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT and TIM5_CHA; the datasheet recommends reserving PA9 and PA10 as the ISP programming interface. |
| 20 | PA10 | bidirectional | GPIO PA10 with alternate functions UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT and TIM6_CHA; the datasheet recommends reserving it with PA9 as the ISP programming interface. |
| 21 | PA11 | bidirectional | GPIO PA11 with alternate functions UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO and TIM4_CHB. |
| 22 | PA12 | bidirectional | GPIO PA12 with alternate functions UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT and SPI0_MOSI. |
| 23 | PA13/SWDIO | bidirectional | GPIO PA13 that serves as the SWD data pin (SWDIO) for debug and programming, also with IR_OUT, UART0_RXD, LVD_OUT and TIM3_ETR. |
| 24 | PA14/SWCLK | bidirectional | GPIO PA14 that serves as the SWD clock pin (SWCLK), also with UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT and PLL_OUT. |
| 25 | PA15 | bidirectional | GPIO PA15 with alternate functions SPI0_CS, UART1_RXD, TIM0_ETR, TIM0_CHA and TIM3_CH1A. |
| 26 | PB03 | bidirectional | GPIO PB03 with alternate functions SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, XTL_OUT and XTH_OUT. |
| 27 | PB04 | bidirectional | GPIO PB04 with alternate functions SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE and TIM3_CH0B. |
| 28 | PB05 | bidirectional | GPIO PB05 with alternate functions SPI0_MOSI, TIM1_BK, PCA_CH1 and UART0_RTS. |
| 29 | PB06 | bidirectional | GPIO PB06 with alternate functions I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA and TIM3_CH0A. |
| 30 | PB07 | bidirectional | GPIO PB07 with alternate functions I2C0_SDA, UART0_RXD, TIM2_CHB and TIM0_CHB; also an LVD monitoring input per the LVD section. |
| 31 | BOOT0 | input | Boot-mode pin sampled at reset: high selects ISP programming mode, low selects user mode executing Flash code with SWD programming available. |
| 32 | DVSS | power_in | Digital ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (incl. AVCC and DVCC) | VCC - VSS | -0.3 | 5.5 | V | 38 | ||
| Voltage difference between supply pins | /ΔVCCx/ | 50 | mV | 38 | |||
| Voltage difference between ground pins | /VSSx - VSS/ | 50 | mV | 38 | |||
| Total current through DVCC/AVCC supply lines (supply current) | IVCC | 300 | mA | 39 | |||
| Total current through VSS ground lines (sink current) | IVSS | 300 | mA | 39 | |||
| Output sink current on any I/O and control pin | IIO | 25 | mA | 39 | |||
| Output current on any I/O and control pin (printed as -25 in max column) | IIO | -25 | mA | 39 | |||
| Injection current on RESETB pin | IINJ(PIN) | -5 | 5 | mA | RESETB pin | 39 | |
| Injection current on XTHI pin (XTH) and XTLI pin (XTL) | IINJ(PIN) | -5 | 5 | mA | XTHI pin of XTH and XTLI pin of XTL | 39 | |
| Injection current on other pins | IINJ(PIN) | -5 | 5 | mA | 39 | ||
| Total injection current on all I/O and control pins | ∑IINJ(PIN) | -25 | 25 | mA | all I/O and control pins | 39 | |
| Storage temperature range | TSTG | -60 | 150 | ℃ | 39 | ||
| Maximum junction temperature | TJ | 105 | ℃ | 39 | |||
| Internal AHB clock frequency | fHCLK | 0 | 48 | MHz | 39 | ||
| Internal APB0 clock frequency | fPCLK0 | 0 | 48 | MHz | 39 | ||
| Internal APB1 clock frequency | fPCLK1 | 0 | 48 | MHz | 39 | ||
| Digital supply voltage | DVCC | 1.8 | 5.5 | V | 39 | ||
| Analog supply voltage | AVCC | 1.8 | 5.5 | V | must be the same as DVCC | 39 | |
| Power dissipation (LQFP32 package) | PD | 357 | mW | TA=85℃, LQFP32 | 39 | ||
| Ambient temperature (maximum power consumption) | TA | -40 | 85 | ℃ | maximum power consumption | 40 | |
| Ambient temperature (low power consumption) | TA | -40 | 105 | ℃ | low power dissipation state | 40 | |
| Junction temperature range | TJ | -40 | 105 | ℃ | 40 | ||
| VCC rising rate | tVcc | 0 | μs/V | 40 | |||
| VCC falling rate | tVcc | 10 | μs/V | 40 | |||
| POR release voltage (power-up) / BOR detection voltage (power-down) | Vpor | 1.45 | 1.5 | 1.65 | V | 40 | |
| External input voltage range | Vex | 0 | V | 41 | |||
| LVD detection threshold | Vlevel | 1.7 | 1.8 | 1.9 | V | LVD_CR.VTDS=0000 | 41 |
| LVD detection threshold | Vlevel | 1.8 | 1.9 | 2 | V | LVD_CR.VTDS=0001 | 41 |
| LVD detection threshold | Vlevel | 1.9 | 2 | 2.1 | V | LVD_CR.VTDS=0010 | 41 |
| LVD detection threshold | Vlevel | 2 | 2.1 | 2.2 | V | LVD_CR.VTDS=0011 | 41 |
| LVD detection threshold | Vlevel | 2.1 | 2.2 | 2.3 | V | LVD_CR.VTDS=0100 | 41 |
| LVD detection threshold | Vlevel | 2.2 | 2.3 | 2.4 | V | LVD_CR.VTDS=0101 | 41 |
| LVD detection threshold | Vlevel | 2.3 | 2.4 | 2.5 | V | LVD_CR.VTDS=0110 | 41 |
| LVD detection threshold | Vlevel | 2.4 | 2.5 | 2.6 | V | LVD_CR.VTDS=0111 | 41 |
| LVD detection threshold | Vlevel | 2.5 | 2.6 | 2.7 | V | LVD_CR.VTDS=1000 | 41 |
| LVD detection threshold | Vlevel | 2.6 | 2.7 | 2.8 | V | LVD_CR.VTDS=1001 | 41 |
| LVD detection threshold | Vlevel | 2.7 | 2.8 | 2.9 | V | LVD_CR.VTDS=1010 | 41 |
| LVD detection threshold | Vlevel | 2.8 | 2.9 | 3 | V | LVD_CR.VTDS=1011 | 41 |
| LVD detection threshold | Vlevel | 2.9 | 3 | 3.1 | V | LVD_CR.VTDS=1100 | 41 |
| LVD detection threshold | Vlevel | 3 | 3.1 | 3.2 | V | LVD_CR.VTDS=1101 | 41 |
| LVD detection threshold | Vlevel | 3.1 | 3.2 | 3.3 | V | LVD_CR.VTDS=1110 | 41 |
| LVD detection threshold | Vlevel | 3.2 | 3.3 | 3.4 | V | LVD_CR.VTDS=1111 | 41 |
| Internal 2.5V reference voltage | VREF25 | 2.475 | 2.5 | 2.525 | V | 25°C, 3.3V | 41 |
| Internal 2.5V reference voltage | VREF25 | 2.463 | 2.5 | 2.525 | V | -40 |
41 |
| Internal 1.5V reference voltage | VREF15 | 1.485 | 1.5 | 1.515 | V | 25°C, 3.3V | 41 |
| Internal 1.5V reference voltage | VREF15 | 1.477 | 1.5 | 1.519 | V | -40 |
41 |
CAD (KiCad official)
- Symbol:
HC32F030F8TA-LQ32 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
hc32f030f8ta-lq32-etched.step/hc32f030f8ta-lq32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f030f8ta-lq32.step/hc32f030f8ta-lq32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (80 pp, sha256
c1f5c05168fa2ea7, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HC32F030F8TA-LQ32
**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
HC32F030F8TA-LQ32 from XHSC, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCAP | power_out | LDO core-supply output for internal circuits only, requires an external decoupling capacitor of at least 1 µF. |
| 2 | XTHI/PD00 | bidirectional | High-speed crystal oscillator input XTHI (4-32 MHz) shared with GPIO PD00, whose alternate functions are I2C0_SDA and UART1_TXD. |
| 3 | XTHO/PD01 | bidirectional | High-speed crystal oscillator output XTHO (4-32 MHz) shared with GPIO PD01, whose alternate functions are I2C0_SCL, TIM4_CHB and UART1_RXD. |
| 4 | RESETB | input | Active-low reset input, CMOS with a non-disconnectable pull-up (about 80 kΩ), VIL up to 0.3VCC and VIH from 0.7VCC. |
| 5 | AVCC | power_in | Analog supply, 1.8-5.5 V, which must be the same voltage as DVCC (at most 300 mV difference is allowed during power-up and operation). |
| 6 | PA00 | bidirectional | GPIO PA00 that also serves ADC input AIN0, comparator inputs VC0/VC1, and UART1_CTS, TIM0, TIM1 and TIM3 functions. |
| 7 | PA01 | bidirectional | GPIO PA01 that also serves ADC input AIN1, comparator inputs, UART1_RTS, TIM0/TIM1 channels, HCLK_OUT and SPI1_MOSI. |
| 8 | PA02 | bidirectional | GPIO PA02 that also serves ADC input AIN2, comparator inputs, VC1_OUT, UART1_TXD, PCLK_OUT and SPI1_MISO. |
| 9 | PA03 | bidirectional | GPIO PA03 with digital alternate functions UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A and TIM5_CHA. |
| 10 | PA04 | bidirectional | GPIO PA04 with alternate functions SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT and TIM3_CH2B. |
| 11 | PA05 | bidirectional | GPIO PA05 with alternate functions SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT and XTH_OUT. |
| 12 | PA06 | bidirectional | GPIO PA06 with alternate functions SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT and TIM3_GATE. |
| 13 | PA07 | bidirectional | GPIO PA07 with alternate functions SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT and TIM4_CHB. |
| 14 | PB00 | bidirectional | GPIO PB00 with alternate functions PCA_CH2, TIM3_CH1B, TIM5_CHB, RCH_OUT, RCL_OUT and PLL_OUT. |
| 15 | PB01 | bidirectional | GPIO PB01 with alternate functions PCA_CH3, PCLK_OUT, TIM3_CH2B and TIM6_CHB. |
| 16 | DVSS | power_in | Digital ground. |
| 17 | DVCC | power_in | Digital supply, 1.8-5.5 V, with a decoupling capacitor placed as close as possible to the pin. |
| 18 | PA08 | bidirectional | GPIO PA08 with alternate functions UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA and TIM3_BK. |
| 19 | PA09 | bidirectional | GPIO PA09 with alternate functions UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT and TIM5_CHA; the datasheet recommends reserving PA9 and PA10 as the ISP programming interface. |
| 20 | PA10 | bidirectional | GPIO PA10 with alternate functions UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT and TIM6_CHA; the datasheet recommends reserving it with PA9 as the ISP programming interface. |
| 21 | PA11 | bidirectional | GPIO PA11 with alternate functions UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO and TIM4_CHB. |
| 22 | PA12 | bidirectional | GPIO PA12 with alternate functions UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT and SPI0_MOSI. |
| 23 | PA13/SWDIO | bidirectional | GPIO PA13 that serves as the SWD data pin (SWDIO) for debug and programming, also with IR_OUT, UART0_RXD, LVD_OUT and TIM3_ETR. |
| 24 | PA14/SWCLK | bidirectional | GPIO PA14 that serves as the SWD clock pin (SWCLK), also with UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT and PLL_OUT. |
| 25 | PA15 | bidirectional | GPIO PA15 with alternate functions SPI0_CS, UART1_RXD, TIM0_ETR, TIM0_CHA and TIM3_CH1A. |
| 26 | PB03 | bidirectional | GPIO PB03 with alternate functions SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, XTL_OUT and XTH_OUT. |
| 27 | PB04 | bidirectional | GPIO PB04 with alternate functions SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE and TIM3_CH0B. |
| 28 | PB05 | bidirectional | GPIO PB05 with alternate functions SPI0_MOSI, TIM1_BK, PCA_CH1 and UART0_RTS. |
| 29 | PB06 | bidirectional | GPIO PB06 with alternate functions I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA and TIM3_CH0A. |
| 30 | PB07 | bidirectional | GPIO PB07 with alternate functions I2C0_SDA, UART0_RXD, TIM2_CHB and TIM0_CHB; also an LVD monitoring input per the LVD section. |
| 31 | BOOT0 | input | Boot-mode pin sampled at reset: high selects ISP programming mode, low selects user mode executing Flash code with SWD programming available. |
| 32 | DVSS | power_in | Digital ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (incl. AVCC and DVCC) | VCC - VSS | -0.3 | | 5.5 | V | | 38 |
| Voltage difference between supply pins | /ΔVCCx/ | | | 50 | mV | | 38 |
| Voltage difference between ground pins | /VSSx - VSS/ | | | 50 | mV | | 38 |
| Total current through DVCC/AVCC supply lines (supply current) | IVCC | | | 300 | mA | | 39 |
| Total current through VSS ground lines (sink current) | IVSS | | | 300 | mA | | 39 |
| Output sink current on any I/O and control pin | IIO | | | 25 | mA | | 39 |
| Output current on any I/O and control pin (printed as -25 in max column) | IIO | | | -25 | mA | | 39 |
| Injection current on RESETB pin | IINJ(PIN) | -5 | | 5 | mA | RESETB pin | 39 |
| Injection current on XTHI pin (XTH) and XTLI pin (XTL) | IINJ(PIN) | -5 | | 5 | mA | XTHI pin of XTH and XTLI pin of XTL | 39 |
| Injection current on other pins | IINJ(PIN) | -5 | | 5 | mA | | 39 |
| Total injection current on all I/O and control pins | ∑IINJ(PIN) | -25 | | 25 | mA | all I/O and control pins | 39 |
| Storage temperature range | TSTG | -60 | | 150 | ℃ | | 39 |
| Maximum junction temperature | TJ | | | 105 | ℃ | | 39 |
| Internal AHB clock frequency | fHCLK | 0 | | 48 | MHz | | 39 |
| Internal APB0 clock frequency | fPCLK0 | 0 | | 48 | MHz | | 39 |
| Internal APB1 clock frequency | fPCLK1 | 0 | | 48 | MHz | | 39 |
| Digital supply voltage | DVCC | 1.8 | | 5.5 | V | | 39 |
| Analog supply voltage | AVCC | 1.8 | | 5.5 | V | must be the same as DVCC | 39 |
| Power dissipation (LQFP32 package) | PD | | | 357 | mW | TA=85℃, LQFP32 | 39 |
| Ambient temperature (maximum power consumption) | TA | -40 | | 85 | ℃ | maximum power consumption | 40 |
| Ambient temperature (low power consumption) | TA | -40 | | 105 | ℃ | low power dissipation state | 40 |
| Junction temperature range | TJ | -40 | | 105 | ℃ | | 40 |
| VCC rising rate | tVcc | 0 | | | μs/V | | 40 |
| VCC falling rate | tVcc | 10 | | | μs/V | | 40 |
| POR release voltage (power-up) / BOR detection voltage (power-down) | Vpor | 1.45 | 1.5 | 1.65 | V | | 40 |
| External input voltage range | Vex | 0 | | | V | | 41 |
| LVD detection threshold | Vlevel | 1.7 | 1.8 | 1.9 | V | LVD_CR.VTDS=0000 | 41 |
| LVD detection threshold | Vlevel | 1.8 | 1.9 | 2 | V | LVD_CR.VTDS=0001 | 41 |
| LVD detection threshold | Vlevel | 1.9 | 2 | 2.1 | V | LVD_CR.VTDS=0010 | 41 |
| LVD detection threshold | Vlevel | 2 | 2.1 | 2.2 | V | LVD_CR.VTDS=0011 | 41 |
| LVD detection threshold | Vlevel | 2.1 | 2.2 | 2.3 | V | LVD_CR.VTDS=0100 | 41 |
| LVD detection threshold | Vlevel | 2.2 | 2.3 | 2.4 | V | LVD_CR.VTDS=0101 | 41 |
| LVD detection threshold | Vlevel | 2.3 | 2.4 | 2.5 | V | LVD_CR.VTDS=0110 | 41 |
| LVD detection threshold | Vlevel | 2.4 | 2.5 | 2.6 | V | LVD_CR.VTDS=0111 | 41 |
| LVD detection threshold | Vlevel | 2.5 | 2.6 | 2.7 | V | LVD_CR.VTDS=1000 | 41 |
| LVD detection threshold | Vlevel | 2.6 | 2.7 | 2.8 | V | LVD_CR.VTDS=1001 | 41 |
| LVD detection threshold | Vlevel | 2.7 | 2.8 | 2.9 | V | LVD_CR.VTDS=1010 | 41 |
| LVD detection threshold | Vlevel | 2.8 | 2.9 | 3 | V | LVD_CR.VTDS=1011 | 41 |
| LVD detection threshold | Vlevel | 2.9 | 3 | 3.1 | V | LVD_CR.VTDS=1100 | 41 |
| LVD detection threshold | Vlevel | 3 | 3.1 | 3.2 | V | LVD_CR.VTDS=1101 | 41 |
| LVD detection threshold | Vlevel | 3.1 | 3.2 | 3.3 | V | LVD_CR.VTDS=1110 | 41 |
| LVD detection threshold | Vlevel | 3.2 | 3.3 | 3.4 | V | LVD_CR.VTDS=1111 | 41 |
| Internal 2.5V reference voltage | VREF25 | 2.475 | 2.5 | 2.525 | V | 25°C, 3.3V | 41 |
| Internal 2.5V reference voltage | VREF25 | 2.463 | 2.5 | 2.525 | V | -40~85°C, 2.8~5.5V | 41 |
| Internal 1.5V reference voltage | VREF15 | 1.485 | 1.5 | 1.515 | V | 25°C, 3.3V | 41 |
| Internal 1.5V reference voltage | VREF15 | 1.477 | 1.5 | 1.519 | V | -40~85°C, 1.8~5.5V | 41 |
## CAD (KiCad official)
- Symbol: `HC32F030F8TA-LQ32`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `hc32f030f8ta-lq32-etched.step` / `hc32f030f8ta-lq32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f030f8ta-lq32.step` / `hc32f030f8ta-lq32.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893673463689216) (80 pp, sha256 `c1f5c05168fa2ea7`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hc32f030f8ta-lq32-datasheet.pdf)