component

GT7555CDTR

Public Made by Adom

by adom

XBLW Timers / Counters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timinggt7555cdtrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers gt7555cdtr: viewers · Ray 8d ago
gt7555cdtr-etched.glb Publish 0.1.0 · Ray 8d ago
gt7555cdtr-etched.step gt7555cdtr: factory component page (tier=lcsc) · Ray 8d ago
gt7555cdtr-hero.glb gt7555cdtr: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
gt7555cdtr-hero.overlay.json Publish 0.1.0 · Ray 8d ago
gt7555cdtr.glb Publish 0.1.0 · Ray 8d ago
gt7555cdtr.kicad_mod Publish 0.1.0 · Ray 8d ago
gt7555cdtr.kicad_sym Publish 0.1.0 · Ray 8d ago
gt7555cdtr.lbr Publish 0.1.0 · Ray 8d ago
gt7555cdtr.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

GT7555CDTR

XBLW · Timers / Counters · SOP-8

GT7555CDTR from XBLW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground; also the source of the internal discharge N-channel transistor and the bottom of the resistor divider.
2 TRIGGER input Active-low trigger input to comparator B; output goes HIGH when voltage is below 1/3 VDD.
3 OUTPUT output Timer output driver, fully compatible with CMOS, TTL and MOS under 5V.
4 RESET input Active-low flip-flop reset; LOW forces OUTPUT low and turns the discharge switch ON.
5 CONTROL VOLTAGE input Control voltage input at the internal divider node (2/3 VDD threshold reference) for adjusting comparator thresholds.
6 THRESHOLD input Threshold input to comparator A; output goes LOW when voltage is above 2/3 VDD with trigger above 1/3 VDD.
7 DISCHARGE passive Open drain of the internal N-channel discharge switch, used to discharge the external timing capacitor; ON when output is LOW.
8 VDD power_in Positive supply voltage; absolute maximum 18 V, lowest operating voltage 4.5 V.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-8
Category Clock/Timing
Pins 8

CAD (KiCad official)

  • Symbol: GT7555CDTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: gt7555cdtr-etched.step / gt7555cdtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gt7555cdtr.step / gt7555cdtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (9 pp, sha256 515c5f729f06da83, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF